Datasheet

3–22
Another way to access specific location in the RAM during RAM test mode is to write desired value to
AdrCounter of ATF status register. The next RAM test read or write accesses the location pointed by
AdrCounter. AdrCounter contains current RAM address in RAM test mode
During RAM test mode any location inside FIFO can be accessed by writing the address to AdrCounter of
ATF status register. Each read or write accesses the location pointed by AdrCounter and Adrcounter
increments by 1 after each transaction. Set AdrClr of ATF status register clears the AdrCounter to 0 and clear
ConErr of ATF status register to 0. Setting Control1 (bit 4) of ATF status register to 1 writes control bit with
1 for RAM test write transaction.
Set RAMTest (bit 5) of ATF status register to 1 to enable RAM Test mode. A write to Address C0h writes
{Control1, DATA0–DATA31} to the location pointed by AdrCounter. A read from Address C0h reads from
the location pointed by AdrCounter. Control bit value can be determined by checking ConErr (bit 2) and
Control1(bit 4) of ATF status register.
Table 3–17. Control Bit Value
ConErr Control1 Control Bit Value
1 1 0
0 1 1
1 0 1
0 0 0
Another way to read the control bit value is to read the cd bit (bit 1) of the GRF status register before reading
a quadlet from address C0h in RAM test mode. The cd bit contains the control bit value pointed to by the
current address counter.
ATF start address is 0. ITF start address is equal to ATF size. GRF start address is equal to (ATF size + ITF
size). FIFO operation temporarily stops during RAM test mode. Clear RAMTest (bit 5) of ATF status register
to 0 resumes normal FIFO operation.