Datasheet

3–15
Table 3–16. Mux Control Register Description (GPO2 Field)
GPO2 FIELD (BITS 12–15) DESCRIPTION of GPO2 PIN (PIN #50)
0 0 0 0 CYCLEOUT
0 0 0 1 CYDNE
†
0 0 1 0 GRFEMP (synchronous to BCLK)
0 0 1 1 CYCLEOUT
†
0 1 0 0 ATF full (synchronous to BCLK)
0 1 0 1 ATF empty (synchronous to BCLK)
0 1 1 0 ITF full (synchronous to BCLK)
0 1 1 1 ITF empty (synchronous to BCLK)
1 0 0 0 ACKRCV
†
1 0 0 1 (SCLK/2)
1 0 1 0 ArbGp (synchronous to SCLK)
1 0 1 1 FrGp (synchronous to SCLK)
1 1 0 0 RxDta
†
1 1 0 1 Constant zero (drive low)
1 1 1 0 Constant zero (drive low)
1 1 1 1 Constant one (drive high)
†
Synchronous to (SCLK/2)
EXAMPLE:To monitor GRFEMP, ITF full, and CYDNE on the general-purpose output pins, the following
setting for the mux control register may be used:
Mux Control Register = ‘0 0 0 1 0 6 0 0’ h
CYDNE
ITF full
GRFEMPTY
In this case, GPO0 = ‘0000’ b
GPO1 = ‘0110’ b
GPO2 = ‘0001’ b