Datasheet

3–13
3.2.14 Mux Control Register (@44h)
The Mux control register resides in the BCLK domain. The power-up reset value of this register is
0000_0000’h. After reset the GRFEMP, CYDNE, and CYST pins will have the same functionality as the
TSB12LV01A device. Tables 3–14, 3–15, and 3–16 describe the bit fields of this register. A logic high on
each GPO pin indicates that the corresponding internal device event or bus event has taken place. For
example, if the GPO0 field is set to ’0100’ and a high state is seen on pin #48 (GRFEMP/GPO0Z), the ATF
full flag has been set.
Table 3–14. Mux Control Register Description (GPO0 Field)
GPO0 FIELD (BITS 28–31) DESCRIPTION of GPO0 PIN (PIN #48)
0 0 0 0 GRFEMP (synchronous to BCLK)
0 0 0 1 CYDNE
†
0 0 1 0 GRFEMP (synchronous to BCLK)
0 0 1 1 CYCLEOUT
†
0 1 0 0 ATF full (synchronous to BCLK)
0 1 0 1 ATF empty (synchronous to BCLK)
0 1 1 0 ITF full (synchronous to BCLK)
0 1 1 1 ITF empty (synchronous to BCLK)
1 0 0 0 ACKRCV
†
1 0 0 1 (SCLK/2)
1 0 1 0 ArbGp (synchronous to SCLK)
1 0 1 1 FrGp (synchronous to SCLK)
1 1 0 0 RxDta
†
1 1 0 1 Constant zero (drive low)
1 1 1 0 Constant zero (drive low)
1 1 1 1 Constant one (drive high)
†
Synchronous to (SCLK/2)