Datasheet

3–12
Table 3–12. GRF Status Register (Continued)
BITS ACRONYM FUNCTION NAME DESCRIPTION
2 PacCom Packet complete When cd = 1 and PacCom = 1, the next block of data from the GRF is
the last one for the packet. When cd = 1 and PacComp = 0, the next
block of data from the GRF is just one block for the current received
packet.
If the trigger size function is disabled or flush bad packet bit is set, cd =
1 and PacCom is 1. This means each received packet only contains
one block of GRF data. When cd = 0 PacCom is not valid.
3–12 GRFTotal
Count
Total GRF data count
stored in quadlet
GRF stored data count which includes all stored received packets and
internally-generated packet tokens.
13–22 GRFSize GRF size GRF Size = 512–(ATFSize+ITFSize)
GRF Size is the total assigned space for the GRF.
23–31 WriteCount Received data
quadlet count of
next block in GRF
This number is valid only when the cd bit is 1. It indicates the received
data quadlet count of next block. WriteCount does not account for the
packet token quadlet. The packet token is always stored on the top of
each received data block to provide a status report. This allows
software to burst read the next block from the GRF.
If trigger-size function is disabled or flush bad received packets bit is
set:
To read each received packet from GRF, first read GRF status register
and make sure cd = 1 so the packet token is on the top of GRF. Next
perform a burst read from the GRF to read (WriteCount+1) quadlets,
which includes the packet token.
In cases where the trigger size function is enabled and FhBad = 0: read
each block of received data as above, until PacCom is 1, which
indicates that the block is the ending block of the current packet.
3.2.13 Host Control Register (@40h)
The host bus control register resides in the host processor clock (BCLK) domain. All the bits in this register
are R/W with an initial value of 0000_0000’h. Table 3–13 describes the bit fields of this register.
Table 3–13. Host Control Register Description
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 AccsFailINT Access failed
interrupt
This bit is set when a host bus access is attempted to a register in the
SCLK domain when SCLK is not running. To clear this bit, write a 1 to
this bit location; a write of 0 has no effect (unless the regRW bit is set in
the diagnostics register). Reset value = 0.
1 AccsFailM Access failed
interrupt mask
This bit is located in the host clock domain. If set to 1, the AccsFailINT is
enabled. If set to 0, the AccsFailINT is masked off. Reset value = 0
(interrupt masked).
2 LPS_EN LPS enable A write of 1 to this bit will enable generation of LPS (PowerOn signal). A
write of 0 has no effect on LPS_EN. This bit is cleared while SoftReset
bit is set to 1. Reset value = 1.
3 SoftReset Software reset A write of 1 to this bit will generate a reset to the link and FIFO logic,
clear TxAEn, RxAEn, TxIEn, and RxIEn in the control register, and
clear LPS_EN in the this register. This bit remains set until a 0 is written
to it.
This bit does not change any other register values (except for the
specified control register bits, and the bits effected by these bits). Reset
value = 0.
4 – 31 Reserved Reserved Reserved