Datasheet

3–11
Table 3–10. ATF Status Register (Continued)
BITS ACRONYM FUNCTION NAME DESCRIPTION
4 Control Control bit The value of control bit is used to relate the MSB of access RAM
location in RAM test mode. For RAM test mode WRITE– control bit
value concatenated with DATA0 – DATA31, writes to the location
pointed by the AdrCounter. For RAM test mode READ– the read
location is pointed to by the current AdrCounter. The read control
counter bit is compared with control bit (bit 4) of ATF status register, if
it does not match, it sets ConErr to 1.
5 RAMTest RAM test mode When RAM test to 1, all FIFO functions are disabled. Write to or
Read from address 80h writes to or reads from the location pointed to
by AdrCounter. After each write or read, the AdrCounter is increm-
ented by 1. The AdrCounter address range is from 0 to 511. For nor-
mal FIFO operation, clear RAMTest to 0. AdrClr and AdrCounter are
in a don’t care state in this case.
6–14 AdrCounter Address counter Gives the address location
15–22 Reserved Reserved Reserved
23–31 ATFSpace-
Count
ATF space count in
quadlets
ATF available space for loading next packet into ATF. If ATFSpace-
Count is larger than the next packet, then the software can burst
write the next packet into the ATF. It only requires two host bus trans-
actions: one ATF status read and one burst write to ATF.
3.2.11 ITF Status Register (@34h)
The ATF status register allows access to the registers that control or monitor the ATF. All the FIFO flag bits
are read only, and the FIFO control bits are read/write. This register provides RAM test mode Control and
status signals. The initial value of the asynchronous transmit
-FIFO status register is 0000_0000h
Table 3–11. ITF Status Register
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 Full ITF full flag When full is set, the FIFO is full and all subsequent writes are ignored.
1 Empty Empty When empty is set, ITF is empty.
2–22 Reserved Reserved Reserved
23–31 ITFSpace-
Count
ITF space count in
quadlets
ITF available space for loading the next packet to the ITF. If
ITFSpaceCount is larger than the next packet quadlet, then the software
can burst write the next packet into the ITF. It only requires two host bus
transactions: one ITF status read and one burst write to the ITF.
3.2.12 GRF Status Register (@3Ch)
The GRF status register allows access to the registers that control or monitor the GRF. All the FIFO flag bits
are read only, and the FIFO control bits are read/write. The initial value of the GRF status register is
0000_0000h.
Table 3–12. GRF Status Register
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 Empty GRF empty flag When empty is set, the GRF is empty.
1 cd GRF controller bit If cd = 1, the packet token is on the top of GRF and the next GRF read will
be the packet token.