Datasheet

3–10
Table 3–9. PHY-Chip Access Register
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 RdPhy Read PHY-chip
register
When RdPhy is set, the TSB12LV01B sends a read register request
with address equal to phyRgAd to the PHY interface. This bit is cleared
when the request is sent.
1 WrPhy Write PHY-chip
register
When WrPhy is set, the TSB12LV01B sends a write register request
with an address equal to phyRgAd on to the PHY interface. This bit is
cleared when the request is sent.
2–3 Reserved Reserved Reserved
4–7 PhyRgAd PHY-chip-register
address
PhyRgAd is the address of the PHY-chip register that is to be accessed.
8–15 PhyRgData PHY-chip-register
data
PhyRgData is the data to be written to the PHY-chip register indicated
in PhyRgAd.
16–19 Reserved Reserved Reserved
20–23 PhyRxAd PHY-chip-register-
received address
PhyRxAd is the address of the register from which PhyRxData came.
24–31 PhyRxData PHY-chip-register-
received data
PhyRxData contains the data from register addressed by PhyRxAd.
3.2.10 Asynchronous Transmit-FIFO (ATF) Status Register (@30h)
The ATF status register allows access to the registers that control or monitor the ATF. The register is at
address 30h. All the FIFO flag bits are read only, and the FIFO control bits are read/write. This register
provides RAM test mode control and status signals. In a RAMTest read/write mode, the following steps
should be followed:
1. Enable RAMTest mode by setting the RAMTest bit (bit 5 in this register)
2. Set the AdrClr bit in order to clear the RAM internal address counter
3. Perform the host bus read/write access to location 80h. This accesses RAM starting at location
00h. With every read/write access, the RAM internal address counter increments by one.
The initial valve of this register is 0000_0000h.
Table 3–10. ATF Status Register
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 Full ATF full flag When full is set, the FIFO is full. Write operations are ignored.
1 Empty ATF-empty flag When empty is set, the FIFO is empty.
2 ConErr Control bit error Each location in the FIFO is 33-bit wide. The MSB is called the con-
trol bit (cd bit), which is used to indicate the first quadlet of each pack-
et in the ATF or the ITF. If the cd bit is 1, the quadlet at that location is
the first quadlet of the packet in ATF or ITF, or a packet token in the
GRF (packet token quadlet is defined in section 3.3.4). In RAM test
mode, all FIFOs become a RAM. Control bits can be verified indirect-
ly. If ConErr is1, the read value of control bit does not match the write
value, which is defined by the control bit (bit 4 in this register). ConErr
is cleared to 0 by writing a 1 to AdrClr bit or 0 to the RAMTest bit.
3 AdrClr Address clear control Set AdrClr to 1 to clear AdrCounter and ConErr to 0, during the next
RAM access. The RAM test mode accesses location 0. AdrClr clears
itself to 0.