Datasheet

39
Table 37. Node-Address/Transmitter Acknowledge Register Field Descriptions (Continued)
BITS ACRONYM FUNCTION
NAME
DESCRIPTION
513 Trigger Size Trigger size in
quadlets
Trigger size is used to partition a received packet into several smaller blocks
of data. For example: if trigger size = 8, total received packet size (excluding
header CRC and data CRC) = 20 quadlets, the receiver creates 3 blocks of
data in the GRF. Each block starts with a packet token quadlet to indicate
how many quadlets follow this packet token. The first and the second block
have 9 quadlets (counting the packet token quadlet). The third block has 5
quadlets (including a packet token quadlet). Each block triggers one RxDta
interrupt. The purpose of the trigger size function is to allow the receiver to
receive a packet larger than the GRF size. The host bus can read the re-
ceived data when each block is available without waiting for the whole pack-
et to be loaded into the GRF. Host bus latency is therefore reduced. If TrgEn
bit is 0 or FhBad bit is 1 in the control register, the trigger size is ignored.
1422 ATFSize Asynchronous
transmitter
FIFO size
ATFSize allocates ATF space size in quadlets. ATFSize must be less than or
equal to 512, and total transmit FIFO space (ATFSize + ITFSize) must also
be less than or equal to 512.
2331 ITFSize Isochronous
transmitter
FIFO size
ITFSize allocates ITF space size in quadlets. ITFSize must be less than or
equal to 512, and total transmit FIFO space (ATFSize + ITFSize) must also
be less than or equal to 512.
3.2.8 Diagnostic Control Register (@20h)
The diagnostic control and status register allows for the monitoring and control of the diagnostic features
of the TSB12LV01B. The regRW and ENSp bits are read/write. When regRW is cleared, all other bits are
read only. When regRW is set, all bits are read/write.
The initial value of the diagnostic control and status register is 0000_0000h.
Table 38. Diagnostic Control and Status-Register Field Descriptions
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 ENSp Enable snoop When ENSp is set, the receiver accepts all packets on the bus
regardless of the address or format. The receiver uses the snoop
data format defined in Section 4.4.
13 Reserved Reserved Reserved
4 regR/W Register read/write
access
When regR/W is set, most registers become fully read/write.
531 Reserved Reserved Reserved
3.2.9 PHY-Chip Access Register (@24h)
The PHY-chip access register allows access to the registers in the attached PHY chip. The most significant
16 bits send read and write requests to the PHY
-chip registers. The least significant 16 bits are for the
PHY
-chip to respond to a read request sent by the TSB12LV01B. The PHY-chip access register also allows
the PHY-interface to send important information back to the TSB12LV01B. When the PHY-interface sends
new information to the TSB12LV01B, the PHY register-information-receive (PhyRRx) interrupt is set. The
register is at address 24h and is read/write. The initial value of the PHY-chip access register is 0000_0000h.