Datasheet

3–8
3.2.5 Cycle-Timer Register (@14h)
The cycle-timer register contains the seconds_count, cycle_count and cycle_offset fields of the cycle timer.
This register is controlled by the cycle master, cycle source, and cycle timer enable bits of the control
register. This register is read/write and must be written to as a quadlet. The initial value of the Cycle-Timer
register is 0000_0000h.
Table 3–5. Cycle-Timer Register Field Descriptions
BITS ACRONYM FUNCTION NAME DESCRIPTION
0–6 seconds_count Seconds count 1-Hz cycle-timer counter
7–19 cycle_count Cycle count 8,000-Hz cycle-timer counter
20–31 cycle_offset Cycle offset 24.576-MHz cycle-timer counter
3.2.6 Isochronous Receive-Port Number Register (@18h)
The isochronous receive-port number register controls which isochronous channels are received by this
node. If the RAI bit of the control register is set, this register value is a don’t care since all channels are
received. The register is read/write. The initial value of the Isochronous Receive-Port Number register is
0000_0000h.
Table 3–6. Isochronous Receive-Port Number Register Field Descriptions
BITS ACRONYM FUNCTION NAME DESCRIPTION
0–1 TAG1 Tag bit 1 Isochronous data format tag. See IEEE 1394-1995 6.2.3 and IEC
61883.
2–7 IRPort1 Isochronous receive
TAG bits and port 1
channel number
IRPort1 contains the channel number of the isochronous packets the
receiver accepts when IRP1En is set. See Table 4–5 and Table 4–6 for
more information.
8–9 TAG2 Tag bit 2 Isochronous data format tag. See IEEE 1394-1995 6.2.3.
10–15 IRPort2 Isochronous receive
TAG bits and port 2
channel number
IRPort2 contains the channel number of the isochronous packets the
receiver accepts when IRP2En is set (bits 8 and 9 are reserved as TAG
bits). See Table 4–5 and Table 4–6 for more information.
16–30 Reserved Reserved Reserved
31 MonTag Monitor tag enable When MonTag is set, the tag bit comparison is enabled. If both TAGx
and IRPortx match fir port number x, the matching receive isochronous
packet is stored in the GRF.
3.2.7 FIFO Control Register (@1Ch)
The FIFO control register is used to clear the ATF, ITF, GRF, and set up a trigger size for the trigger-size
function. ATF size and ITF size fields are all specified in terms of quadlets.
GRF Size = [512–(ATF size) – (ITF size)] quadlets. This register is read/write. The initial value of this register
is 0000_0000h.
Table 3–7. Node-Address/Transmitter Acknowledge Register Field Descriptions
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 ClrATF Clear asynchronous
transfer FIFO
Writing 1 to this bit automatically clears the ATF to 0. This bit is self
clearing.
1 ClrITF Clear isochronous
transfer FIFO
Writing 1 to this bit automatically clears the ITF to 0. This bit is self
clearing.
2 ClrGRF Clear general receive
FIFO
Writing 1 to this bit automatically clears the GRF to 0. This bit is self
clearing.
3–4 Reserved Reserved Reserved