Datasheet

3–6
Set
Clear
Clk
PhInt Bit
Interrupt Bit (INT)
Other
Interrupts
Interrupt Bit
IntMask Bit
PhInt Bit
PhIntMask Bit
INT
DATA (01)
CS
WR
PhInt Source
SCLK
Q
Figure 3–2. Interrupt Logic Diagram Example
Table 3–4. Interrupt- and Mask-Register Field Descriptions
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 Int Interrupt Int contains the value of all interrupt and interrupt mask bits ORed
together.
1 PhInt Phy chip interrupt When PhInt is set, the PHY chip has signaled an interrupt through the
PHY interface.
2 PhyRRx Phy register
information received
When PhyRRx is set, a register value has been transferred to the PHY
chip access register (offset 24h) from the phy interface.
3 PhRst Phy reset started When PhRst is set, a PHY-layer reconfiguration has started (1394 bus
reset).
4 SIDComp Self ID Complete When SIDComp is set, a complete bus reset process is finished. If the
RxSld bit of the control register (@08h) is set, the GRF contains all
received self-ID packets.
5 TxRdy Transmitter ready When TxRdy is set, the transmitter is idle and ready. If TxRdy is set to 1,
and AckV (bit 31 @04h) remains 0 for a nonbroadcast asynchronous
packet, the transmitter failed arbitration and will arbitrate for the bus
again when the bus is idle.
6 RxDta Receiver has data In normal mode and when set, RxDta indicates that the receiver has
accepted a block of data (if TrgEn = 0, a block of data means a packet)
into the GRF interface. However, during the self-ID portion of a bus
reset, this bit is set after each self-ID process is done.
7 CmdRst Command reset
received
When CmdRst is set, the receiver has been sent a quadlet write request
addressed to the RESET_START CSR register.
8 ACKRCV Receive ACK
packet Interrupt
This interrupt is triggered when an acknowledge packet is received or a
timeout has occurred after an asynchronous packet is sent. To enable
this register, the mask interrupt should be set to 1.
9 – 10 Reserved Reserved Reserved