Datasheet

3–4
3.2.3 Control Register (@08h)
The control register dictates the basic operation of the TSB12LV01B. This register is at address 08h and
is read/write. The initial value is 0000_0000h.
Table 3–3. Control-Register Field Descriptions
BITS ACRONYM FUNCTION NAME DESCRIPTION
0 IdVal ID valid When IdVal is set, the TSB12LV01B accepts packets addressed
to the IEEE 1212 address set (Node Number) in the
node-address register. When IdVal is cleared, the TSB12LV01B
accepts only broadcast packets.
1 RxSId Received self-ID packets When RxSId is set, the self-identification packets generated by
phy chips during bus initialization are received and placed into the
GRF as a single packet. Each self-identification packet is
composed of two quadlets, where the second quadlet is the
logical inverse of the first. If ACK (4 bits) equals 1h, then the data
is good. If ACK equals Dh, then the data is wrong. When RxSld is
set link-on packets and PHY configuration packets are also
received and placed into the GRF. For these packets, only the first
quadlet of each packet is stored in the GRF.
2 BsyCtrl Busy control When this bit is set, this node sends an ack_busy_x acknowledge
packet in response to all received nonbroadcast asynchronous
packets. When this bit is cleared, this node sends an ack_busy_x
acknowledge packet only if the GRF is full (i.e., normal
operation).
3 RAI Received all isochronous
packets
If RAI = 1 and RxIEn = 1, the TSB12LV01B will receive all
isochronous packets into the GRF.
4 RcvCySt Receive cycle start If RcvCySt = 1, the TSB12LV01B will store all received cycle-start
packets in the GRF.
5 TxAEn Transmitter enable When TxAEn is cleared, the transmitter does not arbitrate or send
asynchronous packets. After a bus reset, TxAEn is cleared since
the node number may have changed.
6 RxAEn Receiver enable When RxAEn is cleared, the receiver does not receive any
asynchronous packets. After a bus reset, RxAEn is cleared since
the node number may have changed.
7 TxIEn Transmit isochronous
enable
When TxIEn is cleared, the transmitter does not arbitrate or send
isochronous packets.
8 RxIEn Receive isochronous
enable
When RxIEn is cleared, the receiver does not arbitrate o receive
isochronous packets.
9 AckCEn Ack complete enable When AckCEn is set, the TSB12LV01B sends an ack_complete
code (0001) to the transmit node for receiving a nonbroadcast
write request packet if the GRF is not full and there is no error in
the packet. When AckCEn is cleared, the TSB12LV01B sends an
ack_pending code (0010) for the above condition.
10 RstTx Reset transmitter When RstTx is set, the entire transmitter resets synchronously.
This bit clears itself.
11 RstRx Reset receiver When RstRx is set, the entire receiver resets synchronously. This
bit clears itself.
12 – 19 Reserved Reserved Reserved