Datasheet

3–2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 31
00h
Interrupt
CmdRst
ENSpRdPhy
TxlEn
ATAck
Int IdVal
PhInt RxSId
PhRRx
TxRdy
RxDta PhRst
WrPhy
regRW
TxAEn
RxAEn
RstRx RxlEn
AckCen
RstTx
ITBadF
ATBadF
SntRj
HdrEr
TCErr
CyDne CySec
CySt
CyPnd
CyLst
CArbFl
IArbFl
Full
Empty
Full
Empty
Empty
cd
Control
PhyRgAd PhyRxAd
Version
Node
Address
Control
FIFO
Control
Cycle
Timer
Interrupt
Mask
Isoch Port
Number
Diagnostics
PHY Chip
Access
Reserved
Reserved
ATF Status
(Read/Write)
ITF Status
(Read Only)
Reserved
GRF Status
(Read Only)
Reserved
CyTEn CyMas
CySrc
IRP1En IRP2En
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
28
TrgEn
FhBad
7 Bits
IR Port1
Seconds Count
BsyCtrl
Bus Number
TAG2 TAG1
Rollover @ 8000
Cycle Count
13 Bits Rollover @ 3072 12 Bits
IR Port2
Node Number
Version (3031h)
PhyRgData
Revision (3043h)
Cycle Offset
PhyRxData
ATFSpaceCount
ITFSpaceCount
WriteCount
Root
AckV
RAl
RcvCyst
SIDCom
FrGp
ArbGp
CyTm0
MonTag
ClrGRF
Trigger Size ATFSize ITFSize
ClrITF
CLrATF
ConErr
AdrClr
RAMTest
AdrCounter
PacCom
GRFTotalCnt GRFSize
ACKRCV
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AccFI AccFM LPS SRst
Host
Control
(see Note B)
Mux
Control
(see Note B)
Reserved
Reserved Reserved
GPO2 GPO1 GPO0
Reserved Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved
Reserved Reserved
Reserved
Reserved
44h
CmdRst
Int
PhInt
PhRRx
TxRdy
RxDta PhRst
ITBadF
ATBadF
SntRj
HdrEr
TCErr
CyDne CySec
CySt
CyPnd
CyLst
CArbFl
IArbFl
SIDCom
FrGp
ArbGp
CyTm0
ACKRCV
NOTES: A. All gray areas (bits) are reserved bits.
B. This register is new to the TSB12LV01B and does not exist in the TSB12LV01A.
Figure 3–1. Internal Register Map