Datasheet

3–1
3 Internal Registers
3.1 General
The host-bus processor directs the operation of the TSB12LV01B through a set of registers internal to the
TSB12LV01B itself. These registers are read or written by asserting CS
with the proper address on ADDR0
– ADDR7 and asserting or deasserting WR
depending on whether a read or write is needed. Figure 3–1 lists
the register addresses; subsequent sections describe the function of the various registers.
3.2 Internal Register Definitions
The TSB12LV01B internal registers control the operation of the TSB12LV01B. The bit definitions of the
internal registers are shown in Figure 3–1 and are described in subsections 3.2.1 through 3.2.12.
There are three modes to access the internal TSB12LV01B registers; normal mode, quick mode, and burst
mode. The registers from address 00h to 2Ch are accessed using normal mode as shown in Figures 6–2
and 6–3.
The registers 30h, 34h, 3Ch, 40h, 44h, and C0h may be accessed using quick mode reads as shown in
Figure 6–5.
The register 30h and FIFO location 80h through 9Ch may be accessed using quick mode writes as shown
in Figure 6–4.
NOTE:
The protocols for normal mode and quick mode are exactly the same. The only
difference being that quick mode simply returns CA
quicker.
FIFO location 84h, 8Ch, 94h, 9Ch, A0h, and B0h may be accessed using burst mode writes as shown in
Figure 6–6.
The register C0h may be accessed using burst mode reads as shown in Figure 6–7.