Datasheet

2–3
2.1.6 Cycle Monitor
The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes
chip activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent,
the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the
cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the
cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the
cycle-master bit is set in the control register.
2.1.7 Cyclic Redundancy Check (CRC)
The CRC module generates a 32-bit CRC for error detection. This is done for both the header and data. The
CRC module generates the header and data CRC for transmitting packets and checks the header and data
CRC for received packets. See the IEEE 1394-1995 standard for details on the generation of the CRC (this
is the same CRC used by an IEEE802 LANs and the X3T9.5 FDDI)
.
2.1.8 Internal Registers
The internal registers control the operation of the TSB12LV01B.
2.1.9 Host Bus Interface
The host bus interface allows the TSB12LV01B to be easily connected to most host processors. This host
bus interface consists of a 32-bit data bus and an 8-bit address bus. The TSB12LV01B utilizes cycle-start
and cycle-acknowledge handshake signals to allow the local bus clock and the 1394 clock to be
asynchronous to one another. The host bus interface is capable of running at speeds up to 50 MHz. All bus
signal labeling on the TSB12LV01B host interface use bit#0 to denote the most significant bit (MSB). The
TSB12LV01B is interrupt driven to reduce polling.