Datasheet

2–2
2.1.3 Receiver
The receiver takes incoming data from the PHY interface and determines if the incoming data is addressed
to this node. If the incoming packet is addressed to this node, the CRC of the packet is checked. If the header
CRC is good, the header is confirmed in the GRF. For block and isochronous packets, the remainder of the
packet is confirmed one quadlet at a time. The receiver places a status quadlet in the GRF after the last
quadlet of the packet is confirmed in the GRF. The status quadlet contains the error code for the packet. The
error code is the acknowledge code that was or could have been sent for that packet. For broadcast packets
that do not need an acknowledge packet, the error code is the acknowledge code that would have been sent.
This acknowledge code tells the transaction layer whether or not the data CRC is good or bad. When the
header CRC is bad, the header is flushed and the rest of the packet is ignored. Bad packets are automatically
flushed by the receiver.
When a cycle-start message is received, it is detected and the cycle-start message data is sent to the cycle
timer. The cycle-start messages can be placed in the GRF like other quadlet packets.
2.1.4 Transmit and Receive FIFO Memories
The TSB12LV01B contains two transmit FIFOs (ATF and ITF) and one receive FIFO (GRF). Each of these
FIFOs is one quadlet wide and their length is software-selectable. These software-selectable FIFOs allow
customization of the size of each FIFO for individual applications. The sum of all FIFOs cannot be larger
than 512 quadlets. The transmit FIFOs are write only from the host bus interface, and the receive FIFO is
read only from the host bus interface. FIFO sizes must not be changed on the fly. All transactions must be
ignored and FIFOs cleared before changing the FIFO sizes.
An example of how to use software-adjustable FIFOs follows:
In applications where isochronous packets are large and asynchronous packets are small, the user can set
the ITF to a large size (200 quadlets each) and set the ATF to a smaller size (100 quadlets). This means
212 quadlets are allocated to the GRF. Notice that the sum of all FIFOs is equal to 512 quadlets. Only the
ATF size and the ITF size can be programmed, the remaining space is assigned to the GRF.
2.1.5 Cycle Timer
The cycle timer is used by nodes that support isochronous data transfer. The cycle timer is a 32-bit
cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as
defined in the IEEE 1394-1995 standard. In the TSB12LV01B, the cycle-timer register is implemented in the
cycle timer and is located in IEEE-1212 initial register space at location 200h and can also be accessed
through the local bus at address 14h.
The cycle timer contains the cycle-timer register. The cycle-timer register consists of three fields: cycle
offset, cycle count, and seconds count. The low-order 12 bits of the timer are a modulo 3072 counter, which
increments once every 24.576-MHz clock periods (or 40.69 ns). The next 13 higher-order bits are a count
of 8,000-Hz (or 125-µs) cycles, and the highest 7 bits count seconds.
The cycle timer has two possible sources. First, if the cycle source (CySrc) bit in the configuration register
is set, then the CYCLEIN input pin causes the cycle count field to increment for each positive transition of
the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros. CYCLEIN should only be the source when
the node is cycle master. When the cycle-count field increments, CYCLEOUT is generated. The timer can
also be disabled using the cycle-timer-enable bit in the control register.
The second cycle-source option is when the CySrc bit is cleared. In this state, the cycle-offset field of the
cycle-timer register is incremented by the internal 24.576-MHz clock. The cycle timer is updated by the
reception of the cycle-start packet for the noncycle master nodes. Each time the cycle-offset field rolls over,
the cycle-count field is incremented and the CYCLEOUT signal is generated. The cycle-offset field in the
cycle-start packet is used by the cycle-master node to keep all nodes in phase and running with a nominal
isochronous cycle of 125 µs. The cycle-start bit is set when the cycle-start packet is sent from the
cycle-master node or received by a noncycle-master node.