Datasheet

2–1
2 Architecture
2.1 Functional Block Diagram
The functional block architecture of the TSB12LV01B is shown in Figure 2–1.
Transmitter
Cycle Timer
Cycle Monitor
CRC
Receiver
Internal Configuration Registers (CFR)
GRF
ITF
ATF
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FIFO
Host
Processor
Serial
Bus
LINK CORE
Figure 2–1. TSB12LV01B Block Diagram
2.1.1 Physical Interface
The physical (PHY) interface provides PHY-level services to the transmitter and receiver. This includes
gaining access to the serial bus, sending packets, receiving packets, sending and receiving acknowledge
packets, and reading and writing PHY registers.
The PHY interface module also interfaces to the PHY chip and conforms to the PHY-link interface
specification described in Annex J of the IEEE 1394-1995 standard (refer to Section 7 of this document for
more information).
2.1.2 Transmitter
The transmitter retrieves data from either the ATF or the ITF and creates correctly formatted serial-bus
packets to be transmitted through the PHY interface. When data is present at the ATF interface to the
transmitter, the TSB12LV01B PHY interface arbitrates for the serial bus and sends a packet. When data is
present at the ITF interface to the transmitter, the TSB12LV01B arbitrates for the serial bus during the next
isochronous cycle. The transmitter autonomously sends the cycle-start packets when the chip is a cycle
master. The PHY interface provides PHY-level services to the transmitter and receiver. This includes gaining
access to the serial bus, sending packets, receiving packets, and sending and receiving acknowledge
packets.