Datasheet

1–4
1.3 Terminal Functions
PHY Interface
D0 – D7
CTL0
CTL1
LREQ
SCLK
DATA0 – DATA31
ADDR0 – ADDR7
CS
CA
WR
INT
CYCLEIN
CYCLEOUT
BCLK
RESET
MTEST3
V
CC
GND
Host
Bus
11
20
TSB12LV01B
MTEST2
MTEST1
MTEST0
GRFEMP/GPO0
CYDNE/GPO1
CYST/GPO2
POWERON
Figure 1–1. TSB12LV01B Terminal Functions
Table 1–1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
Host Bus Interface
ADDR0 – ADDR7 22–25
27–30
I Host address bus
ADDR0 is the most significant bit (MSB). Address lines 6 and 7 must
be grounded.
(Note: FIFO space and configuration registers are quadlet-aligned.)
CA 35 O Cycle acknowledge (active low). /CA is a TSB12LV01B control signal
to the host bus. When asserted (low), access to the configuration reg-
isters or FIFO is complete.
CS 34 I Cycle start (active low). /CS is a host bus control signal to indicate the
beginning of an access to the TSB12LV01B configuration registers or
FIFO space.
DATA0 – DATA31 82-85, 87-90
92-95, 97-100
2-5, 7-10
12-15, 17-20
I/O Host data bus
DATA0 is the most significant bit (MSB).
Byte0 (DATA0-DATA7) is the most significant byte.
INT 37 O Interrupt (active low). When /INT is asserted (low), the TSB12LV01B
notifies the host bus that an interrupt has occurred.
WR 36 I Read/write enable. When /CS is asserted (low) and /WR is de-as-
serted (high), a read from the TSB12LV01B is requested by the host
bus controller. To request a write access, /WR must be asserted (low).