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     

SCDS172A - JULY 2004 − REVISED DECEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Low Differential Gain and Phase

= 0.2%, D

= 0.1° Typ)

D Wide Bandwidth (B

= 500 MHz Typ)

D Low Crosstalk (X

TALK

= −80 dB Typ)

D Bidirectional Data Flow, With Near-Zero

Propagation Delay

D Low and Flat ON-State Resistance

= 3 Ω Typ, r

on(flat)

= 1 Ω Typ)

D V

Operating Range From 3 V to 3.6 V

D I

off

Supports Partial-Power-Down Mode

Operation

D Data and Control Inputs Provide

Undershoot Clamp Diode

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Performance Tested Per JESD 22

− 2000-V Human-Body Model

(A114-B, Class II)

− 1000-V Charged-Device Model (C101)

D Suitable for Both RGB and Composite

Video Switching

description/ordering information

The TI video switch TS3V340 is a 4-bit 1-of-2

multiplexer/demultiplexer with a single

switch-enable (EN

) input. When EN is low, the switch is enabled, and the D port is connected to the S port. When

is high, the switch is disabled, and the high-impedance state exists between the D and S ports. The select

(IN) input controls the data path of the multiplexer/demultiplexer.

Low differential gain and phase makes this switch ideal for composite and RGB video applications. The device

has a wide bandwidth and low crosstalk, making it suitable for high-frequency applications as well.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel TS3V340RGYR TF340

SOIC − D

Tube TS3V340D

TS3V340

SOIC − D

Tape and reel TS3V340DR

TS3V340

−40

C to 85

SSOP (QSOP) − DBQ Tape and reel TS3V340DBQR TF340

−40 C to 85 C

TSSOP − PW

Tube TS3V340PW

TF340

TSSOP − PW

Tape and reel TS3V340PWR

TF340

TVSOP − DGV Tape and reel TS3V340DGVR TF340

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D, DBQ, DGV, OR PW PACKAGE

(TOP VIEW)

RGY PACKAGE

(TOP VIEW)

116

GND

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Summary of content (29 pages)

PAGE 1
SCDS172A - JULY 2004 − REVISED DECEMBER 2004 D Low Differential Gain and Phase D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC EN S1D S2D DD S1C S2C DC RGY PACKAGE (TOP VIEW) S1A S2A DA S1B S2B DB VCC D D 1 1 16 15 EN 14 S1D 2 3 13 S2D 12 DD 4 5 6 7 8 GND description/ordering information 9 11 S1C 10 S2C DC D IN S1A S2A DA S1B S2B DB GND IN D D D D, DBQ, DGV, OR PW PACKAGE (TOP VIEW) (DG = 0.
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SCDS172A - JULY 2004 − REVISED DECEMBER 2004 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. This switch maintains isolation during power off.
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SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER DEFINITIONS DESCRIPTION PARAMETER RON Resistance between the D and S ports, with the switch in the ON state IOZ IOS VIN Output leakage current measured at the D and S ports, with the switch in the OFF state VEN CIN Voltage at EN Short-circuit current measured at the I/O pins Voltage at IN Capacitance at the control (EN, IN) inputs COFF Capacitance at the analog I/O port wh
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SCDS172A - JULY 2004 − REVISED DECEMBER 2004 functional diagram (positive logic) 2 4 S1A DA 3 S2A DB 7 5 S1B 6 S2B 9 11 DC 10 DD 12 14 13 IN 1 15 EN 4 Control Logic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 S1C S2C S1D S2D
PAGE 5
SCDS172A - JULY 2004 − REVISED DECEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCDS172A - JULY 2004 − REVISED DECEMBER 2004 electrical characteristics over recommended VCC = 3.3 V 0.3 V (unless otherwise noted)† PARAMETER VIK IIH EN, IN IIL IOZ§ IOS¶ EN, IN Ioff ICC EN, IN ICCD CIN free-air TEST CONDITIONS EN, IN ∆ICC operating EN, IN temperature range, TYP‡ MIN MAX UNIT VCC = 3 V, VCC = 3.6 V, IIN = −18 mA VIN and VEN = 5.5 V −1.8 V ±1 µA VCC = 3.6 V, VCC = 3.
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SCDS172A - JULY 2004 − REVISED DECEMBER 2004 0 0 Phase −10 −1 −2 −20 −3 −30 −4 Y −40 Phase (Deg) Gain (dB) Gain J −5 −50 −60 −6 1 10 100 700 Frequency (MHz) Gain −3 dB at 627 MHz Phase at −3-dB Frequency, −47 Deg Y J Figure 1. Gain/Phase vs Frequency 0 0.09 Differental Gain 0.08 −0.04 0.07 −0.06 0.06 −0.08 0.05 J Differental Phase −0.1 0.04 Y −0.12 0.03 −0.14 0.02 −0.16 0.01 −0.18 0 −0.2 −0.
PAGE 8
0 160 −10 140 −20 120 −30 100 Phase J −40 80 −50 60 Y −60 40 OFF Isolation 20 −70 −80 Phase (Deg) OFF Isolation (dB) SCDS172A - JULY 2004 − REVISED DECEMBER 2004 1 10 100 0 700 Frequency (MHz) Y J OFF Isolation at 10 MHz, −56 dB Phase at 10 MHz, 90 Deg 0 180 −10 160 −20 140 −30 120 100 −40 Phase J −50 80 −60 60 Y Crosstalk −70 40 −80 20 −90 0 1 10 100 Frequency (MHz) Y J Crosstalk at 1
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5 20 4 16 VO 3 12 2 8 rON 1 ON-State Resistance (Ω) Output Voltage (V) SCDS172A - JULY 2004 − REVISED DECEMBER 2004 4 0 0 0 1 2 3 4 5 Input Voltage (V) Figure 5.
PAGE 10
SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω IN 50 Ω VG1 TEST CIRCUIT S1x DUT VS1 VO Dx S2x EN CL (see Note A) VS2 TEST VCC RL CL VS1 VS2 tpds 3.3 V ± 0.3 V 3.3 V ± 0.3 V 75 75 20 pF 20 pF GND VCC VCC GND Output Control (VIN) Analog Output Waveform (VO) RL VCC 50% 50% 0V 90% 90% VOH 0V VOLTAGE WAVEFORMS tpd(s) TIMES NOTES: A.
PAGE 11
SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT IN or EN S1X CL (see Note A) RL DUT DX S2X VI VCC 3.3 V ± 0.3 V TEST tON/tOFF CL (see Note A) RL CL VI 75 W 20 pF VCC RL VCC Output Control (VIN) 50% 50% 0V tON Analog Output Waveform (VO) VO tOFF 90% 90% VOH 0V VOLTAGE WAVEFORMS tON AND tOFF TIMES NOTES: A.
PAGE 12
SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER VBIAS BIAS Network Analyzer (HP8753ES) Sawtooth Waveform Generator P1 P2 VCC S1A DA RL = 150 Ω IN DUT VIN EN VEN NOTE: For additional information on measurement method, refer to the TI application report, Measuring Differential Gain and Phase, literature number SLOA040. Figure 8.
PAGE 13
SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC S1A DA RL = 150 Ω IN DUT VIN EN VEN Figure 9. Test Circuit for Frequency Response (BW) The frequency response is measured at the output of the ON channel. For example, when VIN = 0, VEN = 0, and DA is the input, the output is measured at S1A. All unused analog I/O ports are left open.
PAGE 14
SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC DA S1A RL = 150 Ω IN 50 Ω† VIN EN DUT VEN DB S1B RIN = 10 Ω RL = 150 Ω † A 50-Ω termination resistor is needed for the network analyzer. Figure 10. Test Circuit for Crosstalk (XTALK) The crosstalk is measured at the output of the nonadjacent ON channel.
PAGE 15
SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC S1A DA RL = 150 Ω IN DUT VIN S2A EN RL = 150 Ω 50 Ω† VEN † A 50-Ω termination resistor is needed for the network analyzer. Figure 11. Test Circuit for OFF Isolation (OIRR) The OFF isolation is measured at the output of the OFF channel.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TS3V340DGVR Package Package Pins Type Drawing TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 TS3V340DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TS3V340PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3V340DGVR TVSOP DGV 16 2000 367.0 367.0 35.0 TS3V340DR SOIC D 16 2500 333.2 345.9 28.6 TS3V340PWR TSSOP PW 16 2000 367.0 367.0 35.0 TS3V340RGYR VQFN RGY 16 3000 367.0 367.0 35.
PAGE 20
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.