Datasheet

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PARAMETER MEASUREMENT INFORMATION
t
PZH
t
PZL
C
L
(see Note A)
TEST CIRCUIT
S1
2 × V
DD
Open
GND
R
L
R
L
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 2.5 ns, t
f
≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
50 Ω
V
G1
V
DD
DUT
50 Ω
V
IN
50 Ω
V
G2
50 Ω
V
I
TEST
R
L
S1 V
∆
C
L
V
DD
V
I
t
PLZ
/t
PZL
3.3 V ± 0.3 V 2 × V
DD
200 Ω GND 10 pF 0.3 V
Input Generator
Input Generator
V
O
t
PHZ
/t
PZH
3.3 V ± 0.3 V GND 200 Ω V
DD
10 pF 0.3 V
V
OH
−0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
V
DD
/2
V
DD
/2
Output Control
(V
IN
)
1.25 V
2.5 V
V
OH
V
OL
+0.3 V
V
OH
V
OL
0 V
1.25 V
t
PLZ
t
PHZ
Output
Waveform 2
S1 at GND
(see Note B)
Output
Waveform 1
S1 at 2  V
DD
(see Note B)
V
OL
TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006
(Enable and Disable Times)
Figure 4. Test Circuit and Voltage Waveforms
8
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