Datasheet

0 400 800 1200 1600 2000
0
10
20
30
40
50
60
R
DLY
(k)
DELAY TIME (ns)
VSW
t
DLY
n u VLED +V
IN
n u
VLED
TPS92310
SNVS792 –FEBRUARY 2012 www.ti.com
Zero Crossing Detection
To minimized the switching loss of the external MOSFET, a zero crossing detection circuit is embedded in the
TPS92310. V
LAUX
is AC voltage coupled from V
SW
by means of the transformer, with the lower part of the
waveform clipped by D
ZCD
. V
LAUX
is fed back to the ZCD pin to detect a zero crossing point through a resistor
divider network which consists of R
2
and R
3
. The next turn on time of Q
1
is selected V
SW
is the minimum, an
instant corresponding to a small delay after the zero crossing occurs. (Figure 17) The actual delay time depends
on the drain capacitance of the Q
1
and the primary inductance of the transformer (L
P
). Such delay time is set by
a single external resistor as described in Delay Setting section.
During the off-period at steady state, V
ZCD
reaches its maximum V
ZCD-PEAK
(Figure 14), which is scalable by the
turn ratio of the transformer and the resistor divider network R
2
and R
3
. It is recommended that V
ZCD-PEAK
is set to
3V during normal operation.
Figure 17. Switching Node Waveforms
Delay Time Setting
In order to reduce EMI and switching loss, the TPS92310 can insert a delay between the off-period and the on-
period. The delay time is set by a single resistor which connects across the DLY pin and ground, and their
relationship is shown in Figure 18. The optimal delay time depends on the resonance frequency between L
P
and
the drain to source capacitance of Q
1
(C
DS
). Circuit designers should optimize the delay time according to the
following equation.
(1)
(2)
After determining the delay time, t
DLY
can be implemented by setting R
DLY
according to the following equation:
(3)
where K
DLY
= 32MΩ/ns is a constant.
Figure 18. Delay Time Setting
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