Datasheet

1
2
3
4
8
7
6
5
CS
SS
RTC
RTD
REF
VDD
GD
GND
DGKPackage
(TopView)
CS
SS
RTC
RTD
REF
VDD
GD
GND
DPackage
(TopView)
1
2
3
4
8
7
6
5
( )
RISE CT RTC
t 0.74 C 27pF R= ´ + ´
( )
FALL CT RTD
t 0.74 C 27pF R= ´ + ´
TPS92001, TPS92002
www.ti.com SLUSA24A –FEBRUARY 2010–REVISED NOVEMBER 2010
ORDERING INFORMATION
THRESHOLD
OPERATING ORDERABLE
TRANSPORT
TEMPERATURE PACKAGE DEVICE PINS QUANTITY
TURN- TURN-
MEDIA
RANGE T
A
NUMBER
ON OFF
TPS92001DGK Tube 80
Plastic Small Outline (MSOP)
TPS92001DGKR Tape and Reel 2500
10
TPS92001D Tube 75
Plastic Small Outline (SOIC)
TPS92001DR Tape and Reel 2500
–40°C to 85°C 8 8
TPS92002DGK Tube 80
Plastic Small Outline (MSOP)
TPS92002DGKR Tape and Reel 2500
15
TPS92002D Tube 75
Plastic Small Outline (SOIC)
TPS92002DR Tape and Reel 2500
DEVICE INFORMATION
TPS92001/2
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
This pin is the summing node for current sense feedback, voltage sense feedback (by optocoupler) and slope
compensation. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered
with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to
CS 1 I
GND is discharged by an internal 250ohm on resistance NMOS FET during PWM off time. It offers effective
leading edge blanking, with the delay set by the RC time constant of the feedback resistance from current sense
resistor to CS input and the high frequency filter capacitor at this node to GND.
GND 5 – Reference ground and power ground for all functions.
This pin is the high current power driver output. A minimum series gate resistor of 3.9 Ω is recommended to limit
GD 6 O
the gate drive current when operating with high-bias voltages.
The internal 5-V reference output. This reference is buffered and is available on the REF pin. The REF pin should
REF 8 O
be bypassed with a 0.47-µF ceramic capacitor to GND.
This pin connects to timing resistor R
RTC
, and controls the positive ramp (rise) time of the internal oscillator (see
Equation 1). The positive threshold of the internal oscillator is sensed through inactive timing resistor R
RTD
which
connects to pin RTD and timing capacitor, C
CT
.
RTC 3 I
(1)
This pin connects to timing resistor RTD and controls the negative ramp (fall) time of the internal oscillator (see
Equation 2). The negative threshold of the internal oscillator is sensed through inactive timing resistor R
RTC
which
connects to pin RTC and timing capacitor, C
CT
.
RTD 4 I
(2)
This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 6-µA
current source. Under normal soft-start, the SS pin is discharged to at least 0.4 V and then ramps positive to 1 V
SS 2 I during which time the output driver is held low. As the SS pin charges from 1 V to 2 V, the soft-start is
implemented by an increasing output duty cycle. If the SS pin is taken below 0.5 V, the output driver is inhibited
and held low. The user accessible 5-V voltage reference also goes low and I
VDD
= 100 µA
The power input connection for this device. This pin is shunt regulated at 17.5 V which is sufficiently below the
VDD 7 I
voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1-µF ceramic capacitor.
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Product Folder Link(s): TPS92001 TPS92002