Datasheet

TPS92001, TPS92002
www.ti.com SLUSA24A –FEBRUARY 2010–REVISED NOVEMBER 2010
ELECTRICAL CHARACTERISTICS
V
VDD
= 12 V, C
REF
= 0.47-mF, T
A
= T
J
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY SECTION
VDD Supply clamp I
VDD
= 10 mA 16 17.5 19 V
I
VDD
Supply current No Load 600 900 µA
I
VDD
Supply current startup
(1)
110 µA
TPS92001 110 125
Supply current standby V
VDD
= Start threshold – 300 mv µA
TPS92002 130 170
UNDERVOLTAGE LOCKOUT SECTION
TPS92001 9.4 10.4
Start threshold
TPS92002 14.0 15.6
V
TPS92001 1.65
UVLO hysteresis
TPS92002 6.2
VOLTAGE REFERENCE SECTION
Output voltage I
REF
= 0 mA 4.75 5 5.25 V
Line regulation 10 V ≤ V
VDD
≤ 15 V 2 mV
Load regulation 0 mA ≤ I
REF
≤ 5 mA 2 mV
COMPARATOR SECTION
I
CS
Current sense Output OFF -100 nA
Comparator threshold 0.9 0.95 1 V
GD
DLY
GD propagation delay (No Load) 0.8 V ≤ V
CS
≤ 1.2 V at T
R
= 10 ns 50 100 ns
SOFT START SECTION
V
VDD
= 16 V, V
SS
= 0 V, -40°C ≤ T
A
≤ 85°C -4.9 -7.0 -9.1 µA
I
SS
Soft-start current
V
VDD
= 16 V, V
SS
= 0 V, -40°C ≤ T
A
≤ 85° -4.9 -7.0 -10.0 µA
V
SS
Low-level output voltage V
VDD
= 7.5 V, I
SS
= 200 µA 0.2 V
Shutdown threshold 0.44 0.48 0.52 V
OSCILLATOR SECTION
R
RTC
= 10 kΩ, R
RTD
= 4.32 kΩ, C
CT
=
Switching frequency 90 100 110 kHz
820pF
Frequency change with voltage 10 V ≤ V
VDD
≤ 15 V 0.1 %/V
V
CT(peak)
Timing capacitor peak voltage 3.33 V
V
CT(valley)
Timing capacitor valley voltage 1.67 V
V
CT(p-p)
Timing capacitor peak-to-peak voltage 1.54 1.67 1.80 V
GATE DRIVE SECTION
Power driver V
SAT
low I
GD
= 80 mA (dc) 0.8 1.5 V
Power driver V
SAT
high I
GD
= -40 mA (dc), (V
VDD
– V
GD
) 0.8 1.5 V
Power driver low-voltage during UVLO I
GD
= 20 mA (dc) 1.5 V
D
MIN
Minimum duty cycle V
CS
= 2 V 0%
D
MAX
Maximum duty cycle 70%
t
RISE
Rise Time C
GD
= 1nF 35 ns
t
FALL
Fall Time C
GD
= 1nF 18 ns
(1) Specified by design. Not production tested.
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