Datasheet

+
www.ti.com TPS826xxEVM Schematic
2 TPS826xxEVM Schematic
Figure 1 illustrates the TPS826xxEVM-646 schematic.
NOTE: For reference only; see Table 2 for specific values.
Figure 1. TPS826xxEVM Schematic
3 Connector and Test Point Descriptions
3.1 Input / Output Connectors: TPS826xxEVM
3.1.1 J1 VIN
This header is the positive connection to the input power supply. The power supply must be connected
between J1 and J3 (GND). The leads to the input supply should be twisted and kept as short as possible.
The input voltage must be between 2.3 V and 4.8 V.
3.1.2 J2 S+/S–
J2 S+/S– are the sense connection for the input of the converter. Connect a voltmeter, sense connection
of a power supply, or oscilloscope to this header.
3.1.3 J3 GND
This header is the return connection to the input power supply. Connect the power supply between J3 and
J1 (VIN). The leads to the input supply should be twisted and kept as short as possible. The input voltage
must be between 2.3 V and 4.8 V.
Capacitor C3 compensates for parasitic inductance as a result of the wires from the dc power supply to
the EVM. It is not required in an actual application circuit.
3
SLVU383D–October 2010–Revised November 2011 TPS826xxEVM
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated