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Table Of Contents
TPS7A8101EVM Evaluation Module
1 Introduction
2 Setup
2.1 Input/Output Connector Descriptions
2.1.1 J1 – VIN
2.1.2 J2 – VOUT
2.1.3 J3 – VIN
2.1.4 J4 – VOUT
2.1.5 J5 – ENABLE
2.1.6 J6 – Output Voltage Select
2.1.7 J7 and J8 – GND
3 TPS7A8101 Device Operation
3.1 Test Procedure
3.2 Test Data
3.2.1 PSRR
3.2.2 Start-up
3.2.3 Shutdown
3.2.4 Transient Performance
4 Thermal Guidelines
4.1 Thermal Considerations
5 Board Layout
5.1 Layout
6 Schematic and Bill of Materials
6.1 Schematic
6.2 Bill of Materials
Important Notices
Board Layout
www.ti.com
Figure 7.
Top
Layer
Routing
Figure 8.
Bottom
Layer
Routing
8
TPS7A8101EVM Evaluation
Module
SLVU600
–
December 2011
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2011, Texas
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