Datasheet

t (s) = 170,000 x C
STR NR
(F)
TPS7A8101
SBVS179A DECEMBER 2011REVISED APRIL 2012
www.ti.com
STARTUP
Through a lower resistance, the bandgap reference can quickly charge the noise reduction capacitor (C
NR
). The
TPS7A8101 has a quick-start circuit to quickly charge C
NR
, if present; see the Functional Block Diagrams. At
startup, this quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the
NR pin. The quick-start switch opens approximately 100 ms after any device enabling event, and the resistance
between the bandgap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very
good low-pass (RC) filter. This low-pass filter achieves very good noise reduction for the reference voltage.
Inrush current can be a problem in many applications. The 33-kΩ resistance during the startup period is
intentionally put there to slow down the reference voltage ramp up, thus reducing the inrush current. For
example, the capacitance of connecting the recommended C
NR
value of 0.47 μF along with the 33-kΩ resistance
causes approximately 80-ms RC delay. Startup time with the other C
NR
values can be calculated as:
(2)
Although the noise reduction effect is nearly saturated at 0.47 μF, connecting a C
NR
value greater than 0.47 μF
can help reduce noise slightly more; however, startup time will be extremely long because the quick-start switch
opens after approximately 100 ms. That is, if C
NR
is not fully charged during this 100-ms period, C
NR
finishes
charging through a higher resistance of 250 kΩ, and takes much longer to fully charge.
Note that a low leakage C
NR
should be used; most ceramic capacitors are suitable.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but
increases duration of the transient response. Line transient performance can be improved by using a larger noise
reduction capacitor (C
NR
) and/or bypass capacitor (C
BYPASS
).
UNDERVOLTAGE LOCK-OUT (UVLO)
The TPS7A8101 uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a de-glitch feature so that it typically ignores undershoot transients on
the input if they are less than 50-μs duration.
MINIMUM LOAD
The TPS7A8101 is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from
lower loop gain at very light output loads. The TPS7A8101 employs an innovative low-current mode circuit to
increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation
performance down to zero output current.
THERMAL INFORMATION
Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage
because of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least +35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of +125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A8101 has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS7A8101 into thermal shutdown
degrades device reliability.
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