Datasheet

TPS7A8101
www.ti.com SBVS179A –DECEMBER 2011–REVISED APRIL 2012
INPUT AND OUTPUT CAPACITOR REQUIREMENTS
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1.0-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This
capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if
the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF
input capacitor may be necessary to ensure stability.
The TPS7A8101 is designed to be stable with standard ceramic capacitors of capacitance values 4.7 μF or
larger. This device is evaluated using a 10-μF ceramic capacitor of 10-V rating, 10% tolerance, X5R type, and
0805 size (2.0 mm x 1.25 mm).
X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR
over temperature. Maximum ESR should be less than 1.0 Ω.
OUTPUT NOISE
In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (C
NR
) is used with the
TPS7A8101, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output
resistor divider and the error amplifier input. If a bypass capacitor (C
BYPASS
) across the high-side feedback
resistor (R
1
) is used with the TPS7A8101 in addition to C
NR
, noise from these other sources can also be
significantly reduced.
To maximize noise performance in a given application, use a 0.47-μF noise-reduction capacitor plus a 0.47-μF
bypass capacitor.
BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for V
IN
and V
OUT
, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the
GND pin of the device.
INTERNAL CURRENT LIMIT
The TPS7A8101 internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the
device should not be operated in a current limit state for extended periods of time.
The PMOS pass element in the TPS7A8101 has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting may be appropriate.
SHUTDOWN
The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to IN.
DROPOUT VOLTAGE
The TPS7A8101 uses a PMOS pass transistor to achieve low dropout. When (V
IN
– V
OUT
) is less than the
dropout voltage (V
DO
), the PMOS pass device is in its linear region of operation and the input-to-output
resistance is the R
DS(ON)
of the PMOS pass element. V
DO
scales approximately with output current because the
PMOS device in dropout behaves the same way as a resistor.
As with any linear regulator, PSRR and transient response are degraded as (V
IN
– V
OUT
) approaches dropout.
This effect is shown in Figure 20 and Figure 21 in the Typical Characteristics section.
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