Datasheet
TPS7A8101
GND
EN
FB
IN OUT
V
IN
V
OUT
V
EN
R
1
R
2
NR
C
NR
C
IN
C
OUT
C
BYPASS
V =
OUT
x0.800
(R R
1 2
+ )
R
2
TPS7A8101
SBVS179A –DECEMBER 2011–REVISED APRIL 2012
www.ti.com
APPLICATION INFORMATION
OVERVIEW
The TPS7A8101 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve
wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) at very low
headroom (V
IN
– V
OUT
). A noise reduction capacitor (C
NR
) at the NR pin and a bypass capacitor (C
BYPASS
) bypass
noise generated by the bandgap reference in order to improve PSRR, while a quick-start circuit fast-charges the
noise reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal
protection, and is fully specified from –40°C to +125°C.
Recommended Component Values
Table 1. Recommended Capacitor Values
SYMBOL NAME VALUE
C
IN
Input capacitor 10 µF
C
OUT
Output capacitor 10 µF
C
NR
Noise reduction capacitor between NR and GND 470 nF
C
BYPASS
Noise reduction capacitor across R
1
470 nF
Table 2. Recommended Feedback Resistor Values for Common Output Voltages
V
OUT
R
1
R
2
0.8 V 0 Ω (Short) 10.0 kΩ
1.0 V 2.49 kΩ 10.0 kΩ
1.2 V 4.99 kΩ 10.0 kΩ
1.5 V 8.87 kΩ 10.0 kΩ
1.8 V 12.5 kΩ 10.0 kΩ
2.5 V 21.0 kΩ 10.0 kΩ
3.3 V 30.9 kΩ 10.0 kΩ
5.0 V 52.3 kΩ 10.0 kΩ
TYPICAL APPLICATION CONFIGURATION
Figure 31 illustrates the connections for the device.
Figure 31. Typical Application Circuit
(Adjustable Voltage Version)
The voltage on the FB pin sets the output voltage and is determined by the values of R
1
and R
2
. The values of
R
1
and R
2
can be calculated for any voltage using the formula given in Equation 1:
(1)
Table 2 shows sample resistor values for common output voltages. In Table 2, E96 series resistors are used,
and all values meet 1% of the target V
OUT
, assuming resistors with zero error. For the actual design, pay
attention to any resistor error factors. Using lower values for R
1
and R
2
reduces the noise injected from the FB
pin.
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