Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable SON 8 (3x3)

OUT

FB/SNS

GND

DRBPACKAGE

3mmx3mmSON

(TOPVIEW)

TYPICAL POWER-SUPPLY RIPPLE REJECTION

Typical Application Circuit

100

10 100 1k 10k 100k 1M 10M

Frequency (Hz)

PSRR (dB)

OUT

= 10 mA

OUT

= 100 mA

OUT

= 750 mA

OUT

= 1 A

G103

TPS7A8101

GND

IN OUT

OUT

BYPASS

TPS7A8101

www.ti.com

SBVS179A –DECEMBER 2011–REVISED APRIL 2012

Low-Noise, Wide-Bandwidth, High PSRR,

Low-Dropout 1-A Linear Regulator

FEATURES

DESCRIPTION

The TPS7A8101 low-dropout linear regulator (LDO)

• Low-Dropout 1-A Regulator with Enable

offers very good performance in noise and power-

• Adjustable Output Voltage: 0.8 V to 6.0 V

supply rejection ratio (PSRR) at the output. This LDO

• Wide-Bandwidth High PSRR:

uses an advanced BiCMOS process and a

PMOSFET pass device to achieve very low noise,

– 80 dB at 1 kHz

excellent transient response, and excellent PSRR

– 60 dB at 100 kHz

performance.

– 54 dB at 1 MHz

The TPS7A8101 is stable with a 4.7-μF ceramic

• Low Noise: 23.5 μV

RMS

typical (100 Hz to

output capacitor, and uses a precision voltage

100 kHz)

reference and feedback loop to achieve a worst-case

• Stable with a 4.7-μF Capacitance

accuracy of 3% over all load, line, process, and

temperature variations.

• Excellent Load/Line Transient Response

This device is fully specified over the temperature

• 3% Overall Accuracy (over

range of T

= –40°C to +125°C and is offered in a 3-

Load/Line/Temperature)

mm × 3-mm, SON-8 package with a thermal pad.

• Over-Current and Over-Temperature

Protection

• Very Low Dropout: 170 mV Typical at 1 A

• Package: 3-mm × 3-mm SON-8

APPLICATIONS

• Telecom Infrastructure

• Audio

• High-Speed I/F (PLL/VCO)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

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TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 Low-Noise, Wide-Bandwidth, High PSRR, Low-Dropout 1-A Linear Regulator FEATURES DESCRIPTION • • • The TPS7A8101 low-dropout linear regulator (LDO) offers very good performance in noise and powersupply rejection ratio (PSRR) at the output. This LDO uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance.
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TPS7A8101 SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 THERMAL INFORMATION TPS7A8101 THERMAL METRIC (1) (2) DRB (3) UNITS 8 PINS Junction-to-ambient thermal resistance (4) θJA (5) 45.7 θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (6) 21.3 ψJT Junction-to-top characterization parameter (7) 0.9 ψJB Junction-to-board characterization parameter (8) 21.4 θJCbot Junction-to-case (bottom) thermal resistance (9) 5.
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TPS7A8101 SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 1 mA, VEN = 2.2 V, COUT = 4.7 μF, CNR = 0.01 μF, and CBYPASS = 0 μF, unless otherwise noted. TPS7A8101 is tested at VOUT = 0.8 V and VOUT = 6.0 V. Typical values are at TJ = +25°C.
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TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 FUNCTIONAL BLOCK DIAGRAM OUT IN Current Limit EN Thermal Shutdown UVLO 1.20 V Bandgap FB 33 kW Quick-Start NR 33 kW 225 kW 0.8 V 15 pF Adjustable 58.7 kW TPS7A8101 GND Figure 1. Functional Block Diagram PIN CONFIGURATION DRB PACKAGE 3mm x 3mm SON-8 (TOP VIEW) OUT 1 8 IN OUT 2 7 IN FB/SNS 3 6 NR GND 4 5 EN PIN DESCRIPTIONS PIN NAME EN NO. DESCRIPTION 5 Driving this pin high turns on the regulator.
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TPS7A8101 SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS: TPS7A8101 At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted. LOAD REGULATION LOAD REGULATION UNDER LIGHT LOADS 3.399 3.399 +125°C +85°C +25°C 0°C -40°C 3.366 3.333 VOUT (V) VOUT (V) 3.333 +125°C +85°C +25°C 0°C -40°C 3.366 3.3 3.267 3.3 3.267 3.
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TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS: TPS7A8101 (continued) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
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TPS7A8101 SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS: TPS7A8101 (continued) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted. GROUND PIN CURRENT vs LOAD CURRENT 300 250 250 200 200 IGND (mA) IGND (mA) GROUND PIN CURRENT vs INPUT VOLTAGE 300 150 +125°C +85°C +25°C 0°C -40°C 100 50 0 VOUT = 0.
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TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS: TPS7A8101 (continued) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 100 100 90 90 80 80 70 70 PSRR (dB) PSRR (dB) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
PAGE 10
TPS7A8101 SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS: TPS7A8101 (continued) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
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TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS: TPS7A8101 (continued) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted. STARTUP TIME vs NOISE REDUCTION CAPACITANCE LINE TRANSIENT RESPONSE 1000 7 3.333 VIN (V), 0.5V/div 6 100 10 1 3.3165 5.5 3.30825 VIN = 3.8V ® 4.8V ® 3.8V (1V/div) 5 3.
PAGE 12
TPS7A8101 SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 www.ti.com APPLICATION INFORMATION OVERVIEW The TPS7A8101 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) at very low headroom (VIN – VOUT).
PAGE 13
TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection.
PAGE 14
TPS7A8101 SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 www.ti.com STARTUP Through a lower resistance, the bandgap reference can quickly charge the noise reduction capacitor (CNR). The TPS7A8101 has a quick-start circuit to quickly charge CNR, if present; see the Functional Block Diagrams. At startup, this quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the NR pin.
PAGE 15
TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.
PAGE 16
TPS7A8101 SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 www.ti.com Estimating Junction Temperature Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 5). For backwards compatibility, an older θJC,Top parameter is listed as well.
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TPS7A8101 www.ti.com SBVS179A – DECEMBER 2011 – REVISED APRIL 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (December 2011) to Revision A • Page Added new footnote 2 to Thermal Information table, changed footnote 3 ...........................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS7A8101DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS7A8101DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A8101DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS7A8101DRBT SON DRB 8 250 210.0 185.0 35.
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