Datasheet

160
140
120
100
80
60
40
20
0
q
JA
( C/W)°
0 1 2 3
4 5
6
7
8 9 10
BoardCopperArea( )in
2
R
qJA
+
(
)125
O
C * T
A
)
P
D
P
D
+
ǒ
V
IN
* V
OUT
Ǔ
I
OUT
TPS7A80xx
www.ti.com SBVS135H –JUNE 2010–REVISED JANUARY 2013
Power Dissipation
Transient Response
Knowing the device power dissipation and proper
As with any regulator, increasing the size of the
sizing of the thermal plane that is connected to the
output capacitor reduces over/undershoot magnitude
tab or pad is critical to avoiding thermal shutdown
but increases duration of the transient response.
and ensuring reliable operation.
Undervoltage Lock-Out (UVLO)
Power dissipation of the device depends on input
voltage and load conditions and can be calculated
The TPS7A80xx utilizes an undervoltage lock-out
using Equation 4:
circuit to keep the output shut off until the internal
circuitry is operating properly. The UVLO circuit has a
(4)
de-glitch feature so that it typically ignores
undershoot transients on the input if they are less Power dissipation can be minimized and greater
than 50μs duration. efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
Minimum Load
On the SON (DRB) package, the primary conduction
The TPS7A80xx is stable and well-behaved with no
path for heat is through the exposed pad to the
output load. Traditional PMOS LDO regulators suffer
printed circuit board (PCB). The pad can be
from lower loop gain at very light output loads. The
connected to ground or be left floating; however, it
TPS7A80xx employs an innovative low-current mode
should be attached to an appropriate amount of
circuit to increase loop gain under very light or no-
copper PCB area to ensure the device does not
load conditions, resulting in improved output voltage
overheat. The maximum junction-to-ambient thermal
regulation performance down to zero output current.
resistance depends on the maximum ambient
temperature, maximum device junction temperature,
THERMAL INFORMATION
and power dissipation of the device and can be
calculated using Equation 5:
Thermal Protection
Thermal protection disables the output when the
(5)
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
Knowing the maximum R
θJA
, the minimum amount of
temperature cools to approximately +140°C the
PCB copper area needed for appropriate heatsinking
output circuitry is again enabled. Depending on power
can be estimated using Figure 33.
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage because of
overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including heatsink), increase the ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This
configuration produces a worst-case junction
Note: θ
JA
value at board size of 9in
2
(that is, 3in ×
temperature of +125°C at the highest expected
3in) is a JEDEC standard.
ambient temperature and worst-case load.
Figure 33. θ
JA
vs Board Size
The internal protection circuitry of the TPS7A80xx
has been designed to protect against overload
Figure 33 shows the variation of θ
JA
as a function of
conditions. It was not intended to replace proper
ground plane copper area in the board. It is intended
heatsinking. Continuously running the TPS7A80xx
only as a guideline to demonstrate the effects of heat
into thermal shutdown degrades device reliability.
spreading in the ground plane and should not be
used to estimate actual thermal performance in real
application environments.
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