Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- Added CFF test condition and table note to Electrical Characteristics ELECTRICAL CHARACTERISTICS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATIONS
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- Revision History

TPS7A7100
www.ti.com
SBVS189E –MARCH 2012–REVISED SEPTEMBER 2013
THERMAL INFORMATION
TPS7A7100
(3)
THERMAL METRIC
(1)(2)
RGW (QFN) RGT (QFN) UNITS
20 PINS 16 PINS
θ
JA
Junction-to-ambient thermal resistance
(4)
35.7 44.6
θ
JCtop
Junction-to-case (top) thermal resistance
(5)
33.6 54.3
θ
JB
Junction-to-board thermal resistance
(6)
15.2 17.2
°C/W
ψ
JT
Junction-to-top characterization parameter
(7)
0.4 1.1
ψ
JB
Junction-to-board characterization parameter
(8)
15.4 17.2
θ
JCbot
Junction-to-case (bottom) thermal resistance
(9)
3.8 3.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on printed circuit board (PCB) copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the RGW package is derived by thermal simulations based on JEDEC-standard methodology as specified in the
JESD51 series. The following assumptions are used in the simulations:
(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4 × 4 thermal via array.
ii. RGT: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.
(b) i. RGW: Both the top and bottom copper layers have a dedicated pattern for 4% copper coverage.
ii .RGT: Both the top and bottom copper layers have a dedicated pattern for 5% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area.
To understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction
Temperature sections.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θ
JA
using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θ
JA
using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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