Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- Added CFF test condition and table note to Electrical Characteristics ELECTRICAL CHARACTERISTICS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATIONS
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- Revision History

P
D
+
ǒ
V
IN
* V
OUT
Ǔ
I
OUT
TPS7A7100
SBVS189E –MARCH 2012–REVISED SEPTEMBER 2013
www.ti.com
Powering on the device with the enable pin, or increasing the input voltage above the minimum operating voltage
while a low-impedance short exists on the output of the device, may result in a sequence of high-current pulses
from the input to the output of the device. The energy consumed by the device is minimal during these events;
therefore, there is no failure risk. Additional input capacitance helps to mitigate the load transient requirement of
the upstream supply during these events.
ENABLE AND SHUTDOWN THE DEVICE
The EN pin switches the enable and disable (shutdown) states of the TPS7A7100. A logic high input at the EN
pin enables the device; a logic low input disables the device. When disabled, the device consumption current is
reduced.
POWER GOOD
The TPS7A7100 has a power good function that works with the PG output pin. When the output voltage
undershoots the threshold voltage V
IT(PG)
during normal operation, the PG open-drain output turns from a high-
impedance state to a low-impedance state. When the output voltage exceeds the V
IT(PG)
threshold by an amount
greater than the PG hysteresis, V
hys(PG)
, the PG open-drain output turns from a low-impedance state to high-
impedance state. By connecting a pull-up resistor (usually between OUT and PG), any downstream device can
receive an active-high enable logic signal.
When setting the output voltage to less than 1.8 V and using a pull-up resistor between OUT and PG, depending
on the downstream device specifications, the downstream device may not accept the PG output as a valid high-
level logic voltage. In such cases, put a pull-up resistor between IN and PG, not between OUT and PG.
Figure 19 shows the open-drain output drive capability. The on-resistance of the open-drain transistor is
calculated using Figure 19, and is approximately 200 Ω. Any pull-up resistor greater than 10 kΩ works fine for
this purpose.
THERMAL INFORMATION
Thermal Protection
The thermal protection feature disables the output when the junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This thermal limit protects the device from damage as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least +35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of +125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A7100 has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS7A7100 into thermal shutdown
degrades device reliability.
Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 1:
(1)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS7A7100