Datasheet

Vout

Iout

Thermal Guidelines and Layout Recommendations

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NOTE: Blue – VOUT, Green – IOUT

Figure 2. Load-Step and Transient Response

5 Thermal Guidelines and Layout Recommendations

Thermal management is a key component of design of any power converter and is especially important

when the power dissipation in the low-dropout (LDO) regulator is high. Use the following formula to

approximate the maximum power dissipation for the particular ambient temperature:

= T

+ P

× θ

Where T

is the junction temperature, T

is the ambient temperature, P

is the power dissipation in the

device (Watts), and θ

is the thermal resistance from junction to ambient. All temperatures are in degrees

Celsius. The maximum silicon junction temperature, T

, must not be allowed to exceed 150°C. The layout

design must use copper trace and plane areas effectively, as thermal sinks, in order not to allow T

exceed the absolute maximum rating under all temperature conditions and voltage conditions across the

part.

The layout designer must carefully consider the thermal design of the PCB for optimal performance over

temperature. For this EVM, Figure 4 shows that the PCB top VOUT plane has six, 6-mil thermal via

connections to the bottom-side copper VOUT plane to dissipate heat. The PCB is a two-layer board with

2-oz. copper on top and bottom layers. The DDA package drawing can be found at the Texas Instruments

Web site in the product folder for the TPS7A7001 LDO.

Table 1 repeats information from the Dissipation Ratings Table of the TPS7A7001 (SBVS134) data sheet

for comparison with the thermal resistance, θ

, calculated for this EVM layout to show the wide variation

in thermal resistances for given copper areas. The High-K value is determined using a standard JEDEC

High-K (2s2p) board having dimensions of 3-inch x 3-inch with 1-oz internal power and ground planes and

2-oz copper traces on top and bottom of the board.

TPS7A7001EVM-065 Evaluation Module SLVU581–January 2012

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