Datasheet

30
35
40
45
50
55
0 200 400 600 800 1000
Thermal Pad Area (sq. mm)
q
JA
(°C/W)
KTT (D2PAK) (JESD 51-3)
PCB
Thermal Land Pad
Exposed Tab
Thermal Via
(a) Before soldering
(b) After soldering
Ground Plane
TPS7A6201-Q1
www.ti.com SLVSAA0B –NOVEMBER 2010–REVISED MARCH 2012
For optimum thermal performance, it is recommended Keeping other factors constant, surface area of the
to use a high K PCB with thermal vias between thermal land pad contributes to heat dissipation only
ground plane and solder pad/ thermal land pad. This to a certain extent. Figure 26 shows variation of θ
JA
is shown in Figure 25 (a) and (b). Further, heat with surface area of the thermal land pad (soldered to
spreading capabilities of a PCB can be considerably the exposed pad) for KTT package.
improved by using a thicker ground plane and a
thermal land pad with a larger surface area.
Figure 26. θ
JA
vs Thermal Pad Area
Figure 25. Using Multilayer PCB and Thermal
Vias For Adequate Heat Dissipation
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