Datasheet

ON
OFF
Charge Pump State
7.8 7.9
Hysteresis
V (V)
IN
VIN
VOUT
VIN-UVLO
5V or 3.3V
Tracking
0
0
ON
OFF
Charge Pump State
9.2
9.6
Hysteresis
V (V)
IN
TPS7A6201-Q1
SLVSAA0B –NOVEMBER 2010–REVISED MARCH 2012 www.ti.com
Low Voltage Tracking
At low input voltages the regulator drops out of
regulation, the output voltage tracks input minus a
voltage based on the load current (I
OUT
) and switch
resistance (R
SW
) as shown in Figure DDD. This
allows for a smaller input capacitor and can possibly
eliminate the need of using a boost convertor during
cold crank conditions.
Figure 19. Charge Pump Operation at Light
Loads
Figure 21.
Figure 20. Charge Pump Operation at Heavy
Loads
Integrated Fault Protection
The device features integrated fault protection to
Low Power Mode
make it ideal for use in automotive applications. In
order to keep the device in safe area of operation
At light loads and high input voltages (V
IN
>~8V such
during certain fault conditions, internal current limit
that charge pump is off) the device operates in Low
protection and current limit fold back are used to limit
Power Mode and the quiescent current consumption
the maximum output current. This protects the device
is reduced to 25µA (typical) as shown in Table 1.
from excessive power dissipation. For example,
during a short circuit condition on the output; current
Table 1. Typical Quiescent Current Consumption
through the pass element is limited to I
CL
to protect
I
OUT
Charge Pump ON Charge Pump OFF
the device from excessive power dissipation.
I
OUT
< ~2mA 25 µA
250 µA
(Light load) (Low Power Mode)
Thermal Shutdown
I
OUT
> ~2mA
280 µA 70 µA
The device incorporates a thermal shutdown (TSD)
(Heavy load)
circuit as a protection from overheating. For
continuous normal operation, the junction
Under Voltage Shutdown
temperature should not exceed TSD trip point. If the
junction temperature exceeds TSD trip point, the
This device has an integrated under voltage lock out
output is turned off. When the junction temperature
(UVLO) circuit to shutdown the output if the input
falls below TSD trip point, the output is turned on
voltage (V
IN
) falls below an internally fixed UVLO
again. This is shown in Figure 22.
threshold level (V
IN-UVLO
) as shown in Figure 21. This
ensures that the regulator is not latched into an
unknown state during low input voltage conditions.
The regulator will normally power up when the input
voltage exceeds V
IN(POWERUP)
threshold.
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