Datasheet

GND
VOUT
VIN nRST
RDELAY/
ENABLE
1
2
3
4
5
GND
VOUT
VIN nRST
RDELAY/
ENABLE
1
2
3
4
5
TPS7A6033-Q1, TPS7A6050-Q1
TPS7A6133-Q1, TPS7A6150-Q1
SLVSA62G –MARCH 2010–REVISED MARCH 2012 www.ti.com
DEVICE INFORMATION
KTT PACKAGE
KVU PACKAGE
(TOP VIEW)
(TOP VIEW)
TERMINAL FUNCTIONS
NO. NAME TYPE DESCRIPTION
Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor is connected
1 VIN I
between VIN pin and GND pin to dampen input line transients.
2 nRST O Reset pin: This is an output pin with an external pull up resistor connected to VOUT pin.
3 GND I/O Ground pin: This is signal ground pin of the IC.
Reset delay timer pin (for TPS7A60xx only): This pin is used to program the reset delay timer using an
RDELAY O
external capacitor (C
DLY
) to ground.
4
Enable pin (for TPS7A61xx only): This is a high voltage tolerant input pin with an internal pull down. A
EN I high input to this pin activates the device and turns the regulator ON. This input can be connected to
VIN terminal for self bias applications. If this pin is not connected, the device will stay disabled.
Regulated output voltage pin: This is a regulated voltage output (V
OUT
= 3.3V or 5V, as applicable) pin
5 VOUT O with a limitation on maximum output current. In order to achieve stable operation and prevent oscillation,
an external output capacitor (C
OUT
) with low ESR is connected between this pin and GND pin.
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Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1