Datasheet

VIN VOUT
GND
RDELAY
nRST
TPS7A60xx
10µF
to
22µF
1µF
to
10µF
1kΩ
to
5kΩ
VIN
VOUT
0.1µF 0.1µF
RESET
100pF
to
100nF
VIN VOUT
GND
EN
nRST
TPS7A61xx
10µF
to
22µF
1µF
to
10µF
1kΩ
to
5kΩ
VIN
VOUT
0.1µF
VEN
0.1µF
RESET
0
0.5
1
1.5
2
2.5
3
3.5
4
0 25 50 75 100 125
Ambient Air Temperature (°C)
JESD 51-5 (KTT)
JESD 51-3 (KVU)
JESD 51-5 (KVU)
JESD 51-3 (KTT)
Power Dissipated (W)
150
TPS7A6033-Q1, TPS7A6050-Q1
TPS7A6133-Q1, TPS7A6150-Q1
SLVSA62G –MARCH 2010–REVISED MARCH 2012 www.ti.com
APPLICATION INFORMATION
Typical application circuits for TPS7A60xx and As I
QUIESCENT
<< I
OUT
, therefore, the term
TPS7A61xx are shown in Figure 12 and Figure 13 I
QUIESCENT
× V
IN
in Equation 2 can be ignored.
respectively. Depending upon an end application,
For device under operation at a given ambient air
different values of external components may be used.
temperature (T
A
), the junction temperature (T
J
) can
A larger output capacitor may be required during fast
be calculated using Equation 3.
load steps in order to prevent reset from occurring. A
T
J
= T
A
+ (θ
JA
× P
D
) (3)
low ESR ceramic capacitor with dielectric of type X5R
or X7R is recommended. Additionally, a bypass
Where,
capacitor can be connected at the output to decouple
θ
JA
= junction to ambient air thermal impedance
high frequency noise as per the end application.
The rise in junction temperature due to power
dissipation can be calculated using Equation 4.
ΔT = T
J
– T
A
= (θ
JA
× P
D
) (4)
For a given maximum junction temperature (T
J-Max
),
the maximum ambient air temperature (T
A-Max
) at
which the device can operate can be calculated using
Equation 5.
T
A-Max
= T
J-Max
– (θ
JA
× P
D
) (5)
Example
If I
OUT
= 100mA, V
OUT
= 5V, V
IN
= 14V, I
QUIESCENT
=
250µA and θ
JA
= 30˚C/W, the continuous power
dissipated in the device is 0.9W. The rise in junction
Figure 12. Typical Application Schematic for
temperature due to power dissipation is 27˚C. For a
TPS7A60xx
maximum junction temperature of 150˚C, maximum
ambient air temperature at which the device can
operate is 123˚C.
For adequate heat dissipation, it is recommended to
solder the power pad (exposed heat sink) to thermal
land pad on the PCB. Doing this provides a heat
conduction path from die to the PCB and reduces
overall package thermal resistance. Power derating
curves for TPS7A60/1xx series of devices in
KTT(D2PAK) and KVU(DPAK) packages are shown
in Figure 14.
Figure 13. Typical Application Schematic for
TPS7A61xx
Power Dissipation and Thermal
Considerations
Power dissipated in the device can be calculated
using Equation 2.
P
D
= I
OUT
× (V
IN
- V
OUT)
) + I
QUIESCENT
× V
IN
(2)
Where,
P
D
= continuous power dissipation
I
OUT
= output current
V
IN
= input voltage
Figure 14. Power Derating Curves
V
OUT
= output voltage
I
QUIESCENT
= quiescent current
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