Datasheet

Programmable
Reset Delay
VTH(POR)= 93% of VOUT
VIN
VOUT
RDELAY
nRST
VTH(RDELAY)
VIN(POWERUP)
POR
6
CDLY 3
t
1 10
-
´
=
´
250µs
(typ)
V
TH(POR)= 93% of VOUT
VIN
VOUT
Internal
Reset
Delay
nRST
V
TH(RDELAY)
VIN(POWERUP)
TPS7A6033-Q1, TPS7A6050-Q1
TPS7A6133-Q1, TPS7A6150-Q1
www.ti.com SLVSA62G –MARCH 2010–REVISED MARCH 2012
DETAILED DESCRIPTION
nRST is asserted high and C
DLY
is discharged
TPS7A60/1xx is a series of monolithic low dropout
through an internal load. This allows C
DLY
to charge
linear voltage regulators with integrated reset
from approximately 0V during the next power cycle. If
functionality. These voltage regulators are designed
no external capacitor is connected, the delay time is
for low power consumption and quiescent current less
preset internally. This is shown in Figure 6.
than 25µA in light load applications. Because of an
integrated reset delay (also called Power-On Reset In TPS7A60xx devices, if C
DLY
capacitor is not
delay), these devices are well suited in power connected to RDELAY pin, reset delay time is set
supplies for microprocessors/ microcontrollers. internally. This is shown in Figure 7.
These devices are available in two fixed output
voltage (3.3V and 5V) versions as follows:
• Programmable reset delay version (TPS7A60xx)
• Enable version (TPS7A61xx)
The following section describes the features of
TPS7A60/1xx voltage regulators in detail.
Reset Delay and Reset Output
Reset delay is implemented when the device starts
up to indicate that output voltage is stable and in
regulation, and also when the output recovers from a
negative voltage spike due to a load step or a dip in
the input voltage for a specified duration. Reset delay
timer is initialized when the voltage at output (V
OUT
)
exceeds 93% of the regulated output voltage (3.3V or
5V, as applicable). The reset output (nRST) is
asserted high after Power-On Reset delay (t
POR
) has
elapsed. If the regulated output voltage falls below
93% of the set level, nRST is asserted low after a
Figure 6. Power Up and Reset Delay Function
short de-glitch time of approximately 5.5µs (typical).
with C
DLY
Capacitor connected to RDELAY Pin for
TPS7A60xx
For TPS7A60xx devices, reset delay time can be
programmed by connecting an external capacitor
(C
DLY
) to RDELAY pin. The delay time is given by
Equation 1:
(1)
Where,
t
POR
= reset delay time in seconds
C
DLY
= reset delay capacitor value in farads, 100
pF to 100 nF
In TPS7A61xx devices, there is no RDELAY pin and
reset delay time is preset internally (250µs typical).
During power up, the regulator incorporates a
protection scheme to limit the current through pass
element and output capacitor. When the input voltage
exceeds a certain threshold (V
IN(POWERUP)
) level, the
output voltage begins to ramp as shown in Figure 6
and Figure 7. When the output voltage reaches
power on reset threshold (V
TH(POR)
) level, a constant
output current charges an external capacitor (C
DLY
) to
an internal threshold (V
TH(RDELAY)
) voltage level. Then,
Figure 7. Power Up and Reset Delay Function
with C
DLY
Capacitor not connected/available in
TPS7A60xx/TPS7A61xx respectively
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