Datasheet

T = T + ( P
J A JA D
q ´ )
P = (V V ) I
D OUT IN OUT
- ´
TPS7A4700
TPS7A4701
www.ti.com SBVS204E –JUNE 2012–REVISED JANUARY 2014
THERMAL INFORMATION
Thermal Protection
The TPS7A470x contains a thermal shutdown protection circuit to turn off the output current when excessive
heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (T
J
) of the main
pass-FET exceeds +170°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on)
when the temperature falls to +150°C (typical). Because the TPS7A470x is capable of supporting high input
voltages, a great deal of power can be expected to be dissipated across the device at low output voltages which
may cause a thermal shutdown. The thermal time-constant of the semiconductor die is fairly short, and thus the
output oscillates on and off at a high rate when thermal shutdown is reached until power dissipation is reduced.
For reliable operation, the junction temperature should be limited to a maximum of +125°C. To estimate the
thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is
triggered using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown
should occur at least +45°C above the maximum expected ambient temperature condition for the application.
This configuration produces a worst-case junction temperature of +125 ° C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A470x is designed to protect against thermal overload conditions.
The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A470x into thermal
shutdown degrades device reliability.
Power Dissipation (P
D
)
Circuit reliability demands that due consideration be given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and proper sizing of the thermal plane. The PCB area around the regulator
should be as free as possible of other heat-generating devices that can cause added thermal stresses.
Power dissipation in the regulator depends on the input to output voltage difference and load conditions. P
D
can
be calculated using Equation 7:
(7)
It is important to note that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input voltage necessary for output
regulation to be obtained.
The primary heat conduction path for the QFN (RGW) package is through the thermal pad to the PCB. The
thermal pad should be soldered to a copper pad area under the device. This pad area should then contain an
array of plated vias that conduct heat to any inner spreading plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (T
J
) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θ
JA
) of the combined PCB and device package and the temperature of the ambient air (T
A
), according to
Equation 8.
(8)
Unfortunately, this thermal resistance (θ
JA
) is highly dependant on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
spreading planes. The θ
JA
recorded in the Thermal Information table is determined by the JEDEC standard,
PCB, and copper-spreading area and is to be used only as a relative measure of package thermal performance.
Note that for a well-designed thermal layout, θ
JA
is actually the sum of the QFN package junction-to-case
(bottom) thermal resistance (θ
JCbot
) plus the thermal resistance contribution by the PCB copper. By knowing
θ
JCbot
, the minimum amount of appropriate heat sinking can be used to estimate θ
JA
with Figure 25. θ
JCbot
can be
found in the Thermal Information table.
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