Datasheet

I =
OUT(t)
C
OUT OUT
´ dV (t)
dt
V
OUT
(t)
R
LOAD
+
R =
DS(ON)
V
DO
I
RATED
TPS7A4700
TPS7A4701
www.ti.com SBVS204E –JUNE 2012–REVISED JANUARY 2014
INTERNAL CURRENT LIMIT (I
CL
)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate at a steady-state current limit. During a current-limit event, the LDO sources
constant current. Therefore, the output voltage falls while load impedance decreases. Note also that when a
current limit occurs while the resulting output voltage is low, excessive power may be dissipated across the LDO,
which results in a thermal shutdown of the output.
DROPOUT VOLTAGE (V
DO
)
Generally speaking, the dropout voltage often refers to the voltage difference between the input and output
voltage (V
DO
= V
IN
– V
OUT
). However, in the Electrical Characteristics V
DO
is defined as the V
IN
– V
OUT
voltage at
the rated current (I
RATED
), where the main current pass-FET is fully on in the Ohmic region of operation and is
characterized by the classic R
DS(ON)
of the FET. V
DO
indirectly specifies a minimum input voltage above the
nominal programmed output voltage at which the output voltage is expected to remain within its accuracy
boundary. If the input falls below this V
DO
limit (V
IN
< V
OUT
+ V
DO
), then the output voltage decreases in order to
follow the input voltage.
Dropout voltage is always determined by the R
DS(ON)
of the main pass-FET. Therefore, if the LDO operates below
the rated current, then the V
DO
for that current scales accordingly. The R
DS(ON)
for the TPS7A470x can be
calculated using Equation 4:
(4)
OUTPUT VOLTAGE ACCURACY
The output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected
nominal output voltage stated as a percent. This accuracy error typically includes the errors introduced by the
internal reference and the load and line regulation across the full range of rated load and line operating
conditions over temperature, unless otherwise specified by the Electrical Characteristics. Output voltage
accuracy also accounts for all variations between manufacturing lots.
STARTUP
Enable (EN) and Under-Voltage Lockout (UVLO)
The TPS7A470x only turns on when both EN and UVLO are above the respective voltage thresholds. The UVLO
circuit monitors input voltage (V
IN
) to prevent device turn-on before V
IN
rises above the lockout voltage. The
UVLO circuit also causes a shutdown when V
IN
falls below lockout. The EN signal allows independent logic-level
turn-on and shutdown of the LDO when the input voltage is present. EN can be connected directly to V
IN
if
independent turn-on is not needed.
Soft-Start and Inrush Current
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO have
achieved threshold voltage. The noise reduction capacitor serves a dual purpose of both governing output noise
reduction and programming the soft-start ramp during turn-on.
Inrush current is defined as the current through the LDO from IN to OUT during the time of the turn-on ramp up.
Inrush current then consists primarily of the sum of load and charge current to the output capacitor. This current
is difficult to measure because the input capacitor must be removed, which is not recommended. However, this
soft-start current can be estimated by Equation 5:
where:
V
OUT
(t) is the instantaneous output voltage of the turn-on ramp,
dV
OUT
(t)/dt is the slope of the V
OUT
ramp, and
R
LOAD
is the resistive load impedance. (5)
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