Datasheet

TPS7A4700
TPS7A4701
SBVS204E –JUNE 2012–REVISED JANUARY 2014 www.ti.com
Table 3 shows the resistor combinations to achieve some standard rail voltages with commercially-available 1%
tolerance resistors. The resulting output voltages will yield a nominal error of < 0.5%.
Table 3. Suggested Resistors for Common Voltage Rails
V
OUT
R
1
, Calculated R
1
, Closest 1% Value R
2
1.4 V 0 Ω 0 Ω ∞
1.8 V 2.782 kΩ 2.8 kΩ 9.76 kΩ
3.3 V 13.213 kΩ 13.3 kΩ 9.76 kΩ
5 V 25.650 kΩ 25.5 kΩ 10 kΩ
12 V 77.032 kΩ 76.8 kΩ 10.2 kΩ
15 V 101.733 kΩ 102 kΩ 10.5 kΩ
18 V 118.276 kΩ 118 kΩ 10 kΩ
24 V 164.238 kΩ 165 kΩ 10.2 kΩ
To achieve higher nominal accuracy, two resistors can be used in the place of R1. Select the two resistor values
such that the sum will result in a value as close as possible to the calculated R1 value.
There are several alternative ways to set the output voltage. The program pins can be pulled low using external
general-purpose input/output pins (GPIOs), or can be hardwired by the given layout of the printed circuit board
(PCB) to set the ANY-OUT voltage. The TPS7A4701 evaluation module (EVM), available for download from
www.ti.com, allows the output voltage to be programmed using jumpers.
CAPACITOR RECOMMENDATION
These LDOs are designed to be stable using low equivalent series resistance (ESR), ceramic capacitors at the
input, output, and at the noise reduction pin (NR, pin 14). Multilayer ceramic capacitors have become the industry
standard for these types of applications and are recommended here, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good
capacitive stability across temperature whereas the use of Y5V-rated capacitors is discouraged precisely
because the capacitance varies so widely. In all cases, ceramic capacitance varies a great deal with operating
voltage and the design engineer should be aware of these characteristics. As a rule of thumb, ceramic capacitors
are recommended to be derated by 50%. The input and output capacitors recommended herein account for a
capacitance derating of 50%.
Attention should be given to the input capacitance to minimize transient input droop during load current steps
because the TPS7A470x has a very fast load transient response. Large input capacitances (greater than 10 µF)
have a good effect and do not affect stability. Note however that simply using large ceramic input capacitances
can also cause unwanted ringing at the output if the input capacitor, in combination with the wire lead
inductance, creates a high-Q peaking effect during transients. For example, a 5-nH lead inductance and a 10-µF
input capacitor form an LC filter with a resonance frequency of 712 kHz at the edge of the control loop
bandwidth. Short, well-designed interconnect leads to the up-stream supply minimize this effect without adding
damping. Damping of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred
milliohms of ESR, in parallel with the ceramic input capacitor.
Input and Output Capacitor Requirements
The TPS7A470x is designed and characterized for operation with ceramic capacitors of 10 µF or greater at the
input and output. Optimal noise performance is characterized using a total output capacitor value of 50 µF. Note
especially that input and output capacitances should be located as near as practical to the respective input and
output pins.
Noise Reduction Capacitor (C
NR
)
The noise reduction capacitor, connected to the NR pin of the LDO, forms an RC filter for filtering out noise that
might ordinarily be amplified by the control loop and appear on the output voltage. Larger capacitances, up to 1
µF, affect noise reduction at lower frequencies while also tending to further reduce noise at higher frequencies.
Note that C
NR
also serves a secondary purpose in programming the turn-on rise time of the output voltage and
thereby controls the turn-on surge current.
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