Datasheet

TPS7A45xx
SLVS720D –JUNE 2008–REVISED AUGUST 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1) (2)
PRODUCT V
OUT
xx is nominal output voltage
15 = 1.5 V, 18 = 1.8 V, 25 = 2.5 V, 33 = 3.3 V, 01 = adjustable
TPS7A45xxyyyz
yyy is package designator (DCQ or KTT)
z is package quantity (R = 2500 for DCQ, 500 for KTT)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating virtual-junction temperature range (unless otherwise noted)
IN –20 V to 20 V
OUT –20 V to 20 V
Input-to-output differential
(2)
–20 V to 20 V
Input voltage range, V
IN
SENSE –20 V to 20 V
ADJ –7 V to 7 V
SHDN –20 V to 20 V
Output short-circuit duration, t
short
Indefinite
Maximum lead temperature (10-s soldering time), T
lead
300°C
Operating virtual junction temperature range, T
J
–40°C to 125°C
Storage temperature range, T
stg
–65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Absolute maximum input-to-output differential voltage cannot be achieved with all combinations of rated IN pin and OUT pin voltages.
With the IN pin at 20 V, the OUT pin may not be pulled below 0 V. The total measured voltage from IN to OUT can not exceed ±20 V.
THERMAL INFORMATION
TPS7A45xx
THERMAL METRIC
(1)(2)
KTT DCQ UNITS
5 PINS 6 PINS
θ
JA
Junction-to-ambient thermal resistance 28.0 50.5
θ
JCtop
Junction-to-case (top) thermal resistance 43.0 31.1
θ
JB
Junction-to-board thermal resistance 17.4 5.1
°C/W
ψ
JT
Junction-to-top characterization parameter 3.9 1.0
ψ
JB
Junction-to-board characterization parameter 9.4 5.0
θ
JCbot
Junction-to-case (bottom) thermal resistance 0.3 —
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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