Datasheet

TPS7A33

SBVS169C –DECEMBER 2011–REVISED FEBRUARY 2013

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THERMAL PROTECTION

Thermal protection disables the output when the junction temperature rises to approximately +170°C, allowing

the device to cool. When the junction temperature cools to approximately +150°C, the output circuitry is enabled.

Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may

cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of

overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate

heatsink. For reliable operation, junction temperature should be limited to a maximum of +125°C. To estimate the

margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal

protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should

trigger at least +35°C above the maximum expected ambient condition of your particular application. This

configuration produces a worst-case junction temperature of +125°C at the highest expected ambient

temperature and worst-case load.

The internal protection circuitry of the TPS7A33 has been designed to protect against overload conditions. It was

not intended to replace proper heatsinking. Continuously running the TPS7A33 into thermal shutdown degrades

device reliability.

SUGGESTED LAYOUT AND SCHEMATIC

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing

currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade

the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with

a low ESR ceramic bypass capacitor with a X5R or X7R dielectric.

It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout shown in

Figure 31 and the schematic shown in Figure 32 have been shown to produce good results and are meant as a

guideline.

Figure 31. PCB Layout Example: Top Layer