Datasheet

TPS799xx
SBVS056J –JANUARY 2005–REVISED AUGUST 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS799xx yyy z XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
(3)
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 1.2V to 4.5V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
(3) For fixed 1.2V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range (unless otherwise noted).
(1)
PARAMETER TPS799xx UNIT
V
IN
range –0.3 to +7.0 V
V
EN
range –0.3 to V
IN
+0.3 V
V
OUT
range –0.3 to V
IN
+0.3 V
Peak output current Internally limited
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, T
J
–55 to +150 °C
Storage junction temperature range , T
STG
–55 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL INFORMATION
TPS799xx
THERMAL METRIC
(1)(2)
UNITS
DRV (6 PINS)
q
JA
Junction-to-ambient thermal resistance 74.2
q
JCtop
Junction-to-case (top) thermal resistance 58.8
q
JB
Junction-to-board thermal resistance 145.9
°C/W
y
JT
Junction-to-top characterization parameter 0.2
y
JB
Junction-to-board characterization parameter 54.4
q
JCbot
Junction-to-case (bottom) thermal resistance 7.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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