Datasheet

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APPLICATION INFORMATION
0.1 µF
BYPASS
OUT
1
3
IN
EN
GND
2
4
5
V
I
V
O
2.2 µF
+
TPS793xx
0.01 µF
External Capacitor Requirements
Board Layout Recommendation to Improve PSRR and Noise Performance
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP
TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006
The TPS793xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive
battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output
noise, low quiescent current (170 µ A typically), and enable-input to reduce supply currents to less than 1 µ A
when the regulator is turned off.
A typical application circuit is shown in Figure 22 .
Figure 22. Typical Application Circuit
A 0.1- µ F or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS793xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
Like all LDOs, the TPS793xx requires an output capacitor connected between OUT and GND to stabilize the
internal control loop. The minimum recommended capacitance is 2.2- µ F. Any 2.2- µ F or larger ceramic capacitor
is suitable, provided the capacitance does not vary significantly over temperature.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS793xx has a BYPASS pin
that is connected to the voltage reference through a 250-k Ω internal resistor. The 250-k Ω internal resistor, in
conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to reduce
the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate
properly, the current flow out of the BYPASS pin must be at a minimum, because any leakage current creates
an IR drop across the internal resistor, thus, creating an output error. Therefore, the bypass capacitor must have
minimal leakage current.
For example, the TPS79328 exhibits only 32 µ V
RMS
of output voltage noise using a 0.1- µ F ceramic bypass
capacitor and a 2.2- µ F ceramic output capacitor. Note that the output starts up slower as the bypass
capacitance increases due to the RC time constant at the BYPASS pin that is created by the internal 250-k Ω
resistor and external capacitor.
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for V
IN
and V
OUT
, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the
GND pin of the device.
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