Datasheet

TPS79201, TPS79225
TPS79228, TPS79230
SLVS337B – MARCH 2001 – REVISED MAY 2002
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8
APPLICATION INFORMATION
The TPS792xx family of low-dropout (LDO) regulators have been optimized for use in noise-sensitive battery-operated
equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current
(170 µA typically), and enable-input to reduce supply currents to less than 1 µA when the regulator is turned off.
A typical application circuit is shown in Figure 22.
0.1 µF
BYPASS
OUT
1
3
IN
EN
GND
2
4
5
V
I
V
O
1 µF
+
TPS792xx
0.01 µF
Figure 22. Typical Application Circuit
EXTERNAL CAPACITOR REQUIREMENTS
A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS792xx,
required for stability and to improve transient response, noise rejection, and ripple rejection. A higher-value electrolytic input
capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches
from the power source.
Like all low dropout regulators, the TPS792xx requires an output capacitor connected between OUT and GND to stabilize
the internal control loop. The minimum recommended capacitance is 1 µF. Any 1 µF or larger ceramic capacitor is suitable.
The device is also stable with a 0.47 µF ceramic capacitor with at least 75 mΩ of ESR.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS792xx has a BYPASS pin which is
connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in conjunction with an
external bypass capacitor connected to the BYPASS pin, creates a low pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the
BYPASS pin must be at a minimum because any leakage current creates an IR drop across the internal resistor thus
creating an output error. Therefore, the bypass capacitor must have minimal leakage current.
For example, the TPS79228 exhibits only 31 µV
RMS
of output voltage noise using a 0.1-µF ceramic bypass capacitor and
a 1-µF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC
time constant at the bypass pin that is created by the internal 250-kΩ resistor and external capacitor.
BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be
designed with separate ground planes for V
IN
and V
OUT
, with each ground plane connected only at the ground pin of the
device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device.