User’s Guide January 2002 Power Management Products Low Power SLVU059
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
DYNAMIC WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 2.7–13.5 V and the output current range of 0 mA to150 mA. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Preface About This Manual This user’s guide describes the TPS78833EVM LDO regulator evaluation module. Each EVM contains an SLVP191 test board with a TPS78833DBV low dropout linear regulator as well as supporting passive components. The SLVP191 test board provides a convenient method of evaluating the performance of the TPS788xx linear regulator family as well as other SOT–23 packaged linear regulators with the same pinout.
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Running Title—Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 TPS788xx Family of LDO Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EVM Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Schematic . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 Introduction This user’s guide describes the TPS78833EVM LDO regulator evaluation module (SLVP191). Each EVM contains an SLVP191 test board with a TPS78833DBV low dropout linear regulator as well as supporting passive components. Topic Page 1.1 TPS788xx Family of LDO Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 1.2 EVM Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 1.3 Schematic . . . . . . . . . . . . . . .
TPS788xx Family of LDO Regulators 1.1 TPS788xx Family of LDO Regulators The TPS788xx family of LDO regulators consists of small SOT–23 packaged regulators capable of delivering 150 mA of output current. The SR pin of the part can be used to control the output voltage slew rate and therefore the in-rush current of the device. In-rush current control is critical for many USB applications. Other features of the part include: - VI(max) = 13.
Schematic 1.3 Schematic Figure 1–1 shows the SLVP191 PCB schematic diagram, which is used in the TPS78833EVM. Figure 1–1. TPS78833EVM Schematic Diagram J2 U1 TPS78833DBV 1 2 R1 3 Not Used C1 1µF EN R2 10 k Ω IN GND OUT ADJ EN J1 SR J4 6 5 R4 4 C2 0.1 µ F VIN VOUT Not Used C3 10 µ F C4 R3 Not Used Not Used J3 GND 1.4 Bill of Materials Table 1–2 lists materials required for the TPS78833 EVMs. Table 1–1.
Board Layout 1.5 Board Layout Figures 1–2 and 1-3 show the board layout for the TPS78833EVM. Figure 1–2. Top Layer Figure 1–3.
Board Layout Figure 1–4.
1-6 Introduction
Chapter 2 EVM Test Setup This chapter provides recommended test equipment and procedure for performing evaluations using the TPS78833EVM. Figure 2–1 shows the test setup. Figure 2–1.
The settings for the test equipment shown in Figure 2–1 are described below: - Power supply set to 5-V and 1-A current limit connected to IN (J2) and GND (J3). - Function generator set to 1 Hz, 25% duty cycle, 0-V to 5-V amplitude square wave (may require setting of 2.5-V square wave and 2.5-V dc offset) with positive side connected to EN (J1) and negative to GND (J4) - Oscilloscope with the time scale set to 10 ms/div, channel 1 connected to OUT (J4), and channel 2 connected to EN (J1).
Chapter 3 Test Results This chapter gives laboratory test results of the TPS78833EVM obtained for the recommended test procedures in Chapter 2. Figure 3–1 shows start up of the TPS78833 device with different capacitors on the SR pin. V O – Output Voltage – V Enable Voltage – V Figure 3–1. Output Voltage, Enable Voltage vs Time (Start-Up) 5 0 C(SR) = 0.01 µF 3 C(SR) = 0.1 µF 2 VI = 4.3 V VO = 3.
3-2 Test Results
