Datasheet

Layout
3-2
3.1 Layout
The EVM PCB consists of two layers of 1.5 oz. copper. The top side
(component) layout of the EVM is shown in Figure 3–1. Large power and
ground planes are used to minimize trace resistance. The input capacitor (C3)
is located close to the input pin. Proper board layout is critical to ensure the
best noise and PSRR performance. The ground of the output capacitor (C4)
is close to the board’s ground connection for improved transient response, and
the bypass capacitor’s (C7) ground has a low impedance connection to the
IC’s ground connection. The top and bottom side layouts are shown in
Figures 3–2 and 3–3 respectively.
Figure 3–1. Top Side Assembly
Figure 3–2. Bottom Side Assembly