Datasheet

TPS78227
GND
EN
IN OUT
V
IN
V
OUT
1 Fm
1 Fm
4.2Vto5.5V 2.7V
On
Off
TPS782xx
www.ti.com SBVS115C –AUGUST 2008–REVISED JANUARY 2014
APPLICATION INFORMATION
The TPS782 series are designed to be stable with
standard ceramic capacitors with values of 1.0μF or
APPLICATION EXAMPLES
larger at the output. X5R- and X7R-type capacitors
The TPS782 family of LDOs is factory-programmable
are best because they have minimal variation in value
to have a fixed output. Note that during startup or
and ESR over temperature. Maximum ESR should be
steady-state conditions, it is important that the EN pin
less than 1.0Ω. With tolerance and dc bias effects,
voltage never exceed V
IN
+ 0.3V.
the minimum capacitance to ensure stability is 1μF.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance (such as PSRR, output
noise, and transient response), it is recommended
that the printed circuit board (PCB) be designed with
separate ground planes for V
IN
and V
OUT
, with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the
output capacitor should connect directly to the GND
pin of the device. High ESR capacitors may degrade
PSRR.
Figure 22. Typical Application Circuit
INTERNAL CURRENT LIMIT
INPUT AND OUTPUT CAPACITOR
The TPS782 is internally current-limited to protect the
REQUIREMENTS
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
Although an input capacitor is not required for
largely independent of output voltage. For reliable
stability, it is good analog design practice to connect
operation, the device should not be operated in a
a 0.1μF to 1.0μF low equivalent series resistance
current limit state for extended periods of time.
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
The PMOS pass element in the TPS782 series has a
sources and improves transient response, noise
built-in body diode that conducts current when the
rejection, and ripple rejection. A higher-value
voltage at OUT exceeds the voltage at IN. This
capacitor may be necessary if large, fast rise-time
current is not limited, so if extended reverse voltage
load transients are anticipated, or if the device is not
operation is anticipated, external limiting to 5% of
located near the power source. If source impedance
rated output current may be appropriate.
is not sufficiently low, a 0.1μF input capacitor may be
necessary to ensure stability.
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