Datasheet

INPUT AND OUTPUT CAPACITOR SHUTDOWN
t=3
10k RW
L
´
10kW +R
L
C
OUT
´
(3)
BOARD LAYOUT RECOMMENDATIONS TO
TPS781
GND
EN
V
SET
IN OUT
V High=V
SET OUT(LOW)
V Low=V
SET OUT(HIGH)
V
IN
V
OUT
1 Fm
1 Fm
4.2Vto5.5V 2.2Vto3.3V
INTERNAL CURRENT LIMIT
TPS781
GND
EN
V
SET
IN OUT
V
IN
V
OUT
1 Fm
1 Fm
4.2Vto5.5V 2.2V
TPS781 Series
www.ti.com ........................................................................................................................................................... SBVS102B – MARCH 2008 – REVISED MAY 2008
REQUIREMENTS
The enable pin (EN) is active high and is compatible
Although an input capacitor is not required for with standard and low-voltage CMOS levels. When
stability, it is good analog design practice to connect shutdown capability is not required, EN should be
a 0.1 µ F to 1.0 µ F low equivalent series resistance connected to the IN pin, as shown in Figure 52 .
(ESR) capacitor across the input supply near the Figure 53 shows both EN and V
SET
connected to IN.
regulator. This capacitor counteracts reactive input The TPS781 series, with internal active output
sources and improves transient response, noise pull-down circuitry, discharges the output to within 5%
rejection, and ripple rejection. A higher-value V
OUT
with a time ( t) shown in Equation 3 :
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or if the device is not
located near the power source. If source impedance
is not sufficiently low, a 0.1 µ F input capacitor may be
necessary to ensure stability.
Where:
R
L
= output load resistance
The TPS781 series are designed to be stable with
standard ceramic capacitors with values of 1.0 µ F or
C
OUT
= output capacitance
larger at the output. X5R- and X7R-type capacitors
are best because they have minimal variation in value
and ESR over temperature. Maximum ESR should be
less than 1.0 Ω . With tolerance and dc bias effects,
the minimum capacitance to ensure stability is 1 µ F.
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance (such as PSRR, output
noise, and transient response), it is recommended
that the printed circuit board (PCB) be designed with
separate ground planes for V
IN
and V
OUT
, with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the
Figure 52. Circuit Showing EN Tied High when
Shutdown Capability is Not Required
output capacitor should connect directly to the GND
pin of the device. High ESR capacitors may degrade
PSRR.
The TPS781 is internally current-limited to protect the
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
largely independent of output voltage. For reliable
operation, the device should not be operated in a
current limit state for extended periods of time.
The PMOS pass element in the TPS781 series has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
Figure 53. Circuit to Tie Both EN and V
SET
High
operation is anticipated, external limiting to 5% of
rated output current may be appropriate.
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