Datasheet

Powering the MSP430 Microcontroller
LDO
GND
V
IN
V
OUT
1 Fm 1 Fm
MSP430
V
SS
V
CC
I/O
V =3.0V
CC
5mA
Active
Mode
3.0V
1.6 AI
LPM3/SleepMode
m
Q
TPS781
GND
V
IN
V
OUT
MSP430
V
SS
V
CC
I/O
V =3.6V
CC
5mA
Active
Mode
700nAI
LPM3/SleepMode
Q
V =2.2V
CC
Current
1 Fm 1 Fm
2.2Vto3.6V
V
SET
TPS781 Series
SBVS102B – MARCH 2008 – REVISED MAY 2008 ........................................................................................................................................................... www.ti.com
Several versions of the TPS781 are ideal for
powering the MSP430 microcontroller . Table 3 shows
potential applications of some voltage versions.
Table 3. Typical MSP430 Applications
V
OUT(HIGH)
V
OUT(LOW)
DEVICE (TYP) (TYP) APPLICATION
V
OUT, MIN
> 1.800V
required by many
MSP430s. Allows
TPS781360200 3.6V 2.0V
lowest power
consumption
operation.
V
OUT, MIN
> 2.200V
required by some
TPS781360220 3.6V 2.2V
MSP430s FLASH
operation.
V
OUT, MIN
> 2.700V
required by some
TPS781360300 3.6V 3.0V
MSP430s FLASH
operation.
Figure 50. Typical LDO without DVS
V
OUT, MIN
< 3.600V
required by some
TPS781360220 3.6V 2.2V MSP430s. Allows
highest speed
operation.
The TPS781 family offers many output voltage
versions to allow designers to optimize the supply
voltage for the processing speed required of the
MSP430. This flexible architecture minimizes the
supply current consumed by the particular MSP430
application. The MSP430 total system power can be
reduced by substituting the 1 µ A I
Q
TPS781 series
LDO in place of an existing, older-technology LDO.
Additionally, DVS allows for increasing the clock
speed in active mode (MSP430 V
CC
= 3.6V). The
3.6V V
CC
reduces the MSP430 time in active mode.
In low-power mode, MSP430 system power can be
further reduced by lowering the MSP430 V
CC
to 2.2V
in sleep mode.
Key features of the TPS781 series are an ultralow
quiescent current (1 µ A), DVS, and miniaturized
packaging. The TPS781 family are available in
Figure 51. TPS781 with Integrated DVS
SON-6 and TSOT-23 packages. Figure 50 shows a
typical MSP430 circuit powered by an LDO without
DVS. Figure 51 is an MSP430 circuit using a TPS781
The other benefit of DVS is that it allows a higher V
CC
LDO that incorporates an integrated DVS, thus
voltage on the MSP430, increasing the clock speed
simplifying the circuit design. In a circuit without DVS,
and reducing the active mode dwell time.
as Figure 50 illustrates, V
CC
is always at 3.0V. When
the MSP430 goes into sleep mode, V
CC
remains at
3.0V; if DVS is applied, V
CC
could be reduced in
sleep mode. In Figure 51 , the TPS781 LDO with
integrated DVS maintains 3.6V V
CC
until a logic high
signal from the MSP430 forces V
OUT
to level shift
V
OUT
from 3.6V down to 2.2V; thus reducing power in
sleep mode.
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