Datasheet

       
       
    
SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004
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5
TPS777xx RESET timing diagram
(1)
V
res
is the minimum input voltage for a valid RESET
. The symbol V
res
is not currently listed within EIA or JEDEC standards for semiconducto
r
symbology.
V
I
V
res
(1)
V
res
t
t
t
V
O
Threshold
Voltage
RESET
Output
200 ms
Delay
200 ms
Delay
Output
Undefined
Output
Undefined
V
IT+
(2)
V
IT−
(2)
V
IT−
(2)
V
IT+
(2)
Less than 5% of the
output voltage
(2)
V
IT
−Trip voltage is typically 5% lower than the output voltage (95%V
O
) V
IT−
to V
IT+
is the hysteresis voltage.